SystemC not writing values to my memory module - c++

Question

I am trying to try and implement a memory for RTL simulation but it doesn't seem to be writing the my values to the memory below is the memory module that was written.
#define MEM_SIZE (1 << (10+6))
#include <fstream>
#include <string>
#include "systemc.h"
class MEMORY_RTL: public sc_module {
public:
sc_in<sc_logic> Clk;
sc_in<sc_logic> Ren, Wen;
sc_in<unsigned int> Addr;
sc_in<unsigned int> DataIn;
sc_out<unsigned int> DataOut;
sc_out<sc_logic> Ack;
unsigned int mem[MEM_SIZE];
SC_HAS_PROCESS(MEMORY_RTL);
MEMORY_RTL(sc_module_name name, std::string memInitFilename) : sc_module(name) {
SC_METHOD(rtl);
sensitive << Clk.pos();
}
void rtl();
};
void MEMORY_RTL:: rtl()
{
// std::cout << "Clk : " << Clk.read() << " ," << std::endl;
// std::cout << "Ren : " << Ren.read() << " ," << std::endl;
// std::cout << "Wen : " << Wen.read() << " ," << std::endl;
// std::cout << "Addr : " << Addr.read() << " ," << std::endl;
// std::cout << "InData : " << DataIn.read() << " ," << std::endl;
// std::cout << std::endl;
int addr = Addr.read();
if (addr < MEM_SIZE)
{
Ack.write(SC_LOGIC_1);
if (Ren.read() == SC_LOGIC_1)
{
DataOut.write(mem[addr]);
}
else if (Wen.read() == SC_LOGIC_1)
{
int data = DataIn.read();
mem[addr] = data;
}
}
else
{
Ack.write(SC_LOGIC_0);
}
}
and this is my attempt to write my values into the memory module,
#define MEMORY_SIZE (1 << (10+6))
#include <fstream>
#include <string>
#include "systemc.h"
#include "simple_mem_if.h"
#include "MEMORY_RTL.h"
class memory: public sc_module, public simple_mem_if {
public:
sc_signal<sc_logic> clk;
sc_signal<sc_logic> ren, wen;
sc_signal<unsigned int> addr;
sc_signal<unsigned int> dataIn;
sc_signal<unsigned int> dataOut;
sc_signal<sc_logic> ack;
// constructor
memory(sc_module_name name, std::string memfile);
SC_HAS_PROCESS(memory);
MEMORY_RTL *memory_rtl;
// declaration of simple_mem_if functions
virtual bool Read(unsigned int addr, unsigned int& data);
virtual bool Write(unsigned int addr, unsigned int data);
void oscillator();
private:
void ReadText();
std::string memfile;
};
memory::memory(sc_module_name name, std::string memfile)
{
this->memfile = memfile;
SC_THREAD(oscillator);
memory_rtl = new MEMORY_RTL("mem_rtl", memfile);
memory_rtl -> Clk(clk);
memory_rtl -> Ren(ren);
memory_rtl -> Wen(wen);
memory_rtl -> Addr(addr);
memory_rtl -> DataIn(dataIn);
memory_rtl -> DataOut(dataOut);
memory_rtl -> Ack(ack);
ReadText();
}
void memory:: ReadText()
{
ifstream memfileStream(memfile);
std::string entry = "";
int i = 0;
// iterate until we run out of memory or the file ends
for (; i<MEMORY_SIZE; i++) {
// get a token, delimited by a space
if (getline(memfileStream, entry, ' ')) {
// turn the token into an int and save it
Write(i, std::stoi(entry));
}
else {
// leave the loop when the file ends
break;
}
// wait();
} // for
// if the init file isn't big enough to initialize all memory locations,
// fill the rest with zeroes
for (; i<MEMORY_SIZE; i++) Write(i, 0);
}
bool memory:: Read(unsigned int addr, unsigned int& data)
{
// Read the data from the memory
this->ren.write(SC_LOGIC_1);
this->wen.write(SC_LOGIC_0);
this->addr.write(addr);
data = this->dataOut.read();
// wait();
// data = mem[addr];
// sc_logic acknowledgement = this->ack.read();
// return acknowledgement == SC_LOGIC_1;
return true;
}
bool memory:: Write(unsigned int addr, unsigned int data)
{
// Read the data from the memory
this->ren.write(SC_LOGIC_0);
this->wen.write(SC_LOGIC_1);
this->addr.write(addr);
this->dataIn.write(data);
return true;
}
void memory::oscillator() {
while(true) {
clk.write(SC_LOGIC_0);
wait(5, SC_NS);
clk.write(SC_LOGIC_1);
wait(5, SC_NS);
}
}
The following is what I am expecting when I ran my simulation without using the MEMORY_RTL module.
Initial memory state:
6509 7005 6984 6949 7929 6558 7591 7332 7598 6494 7266 6480 8608 6481 7394 7894 8215 6394 8446 6876 6635 6840 8250 6177 6549 7524 8766 6797 6858 6586 7675 7147 6358 7054 8055 8037 6662 7652 6426 7197 6300 8954 6699 7061 7710 7620 7098 9250 7794 6264 6625 7802 7216 6651 8904 7229 7641 7383 6963 6513 6854 7225 6851 6522
Info: /OSCI/SystemC: Simulation stopped by user.
Simulated for 0 s
Final memory state:
7814 7416 6614 6938 8404 6406 7721 7256 7610 7183 7333 7109 7438 9408 9407 9226 8331 9076 8226 8640 9377 9522 8923 9273 9011 8250 7821 9263 8773 8755 8830 8864 8755 8713 8059 8463 8192 8649 9452 8909 8736 7862 8209 9521 9084 7810 8831 8120 8099 9117 9502 8439 8886 9804 7447 8120 9072 9093 9158 9213 10189 8827 9054 9353
but this is what I am getting when I am using it,
Initial memory state:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Info: /OSCI/SystemC: Simulation stopped by user.
Simulated for 0 s
Final memory state:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0