Newbie question about project structures and makefiles - c++

Question

I have a project with this structure
/project
Makefile
.gitignore
/bin
/src
file1.cpp
file2.cpp
file3.cpp
/include
definitions.h
/obj
I played around with the Makefile but I couldn't seem to get what I wanted, first I tried:
CC = g++
CFLAGS = -std=c++2b -Wno-parentheses -Iinclude/
All: build
obj/%.o: src/%.cpp
$(CC) $(CFLAGS) -c $^
build:
$(CC) $(CFLAGS) file1.o file2.o file3.o -o bin/main$(compiler)
but this returned the error
make: *** No rule to make target 'file1.o', needed by 'build'. Stop.
so I tried
CC = g++
CFLAGS = -std=c++2b -Wno-parentheses -Iinclude/
All: build
%.o: src/%.cpp
$(CC) $(CFLAGS) -c $^
build:
$(CC) $(CFLAGS) file1.o file2.o file3.o -o bin/main$(compiler)
and it compiled, putting all the .o files in the main directory, which is unideal. Furthermore, I can't run the binary file unless I specifically opened a terminal in the main directory and enter ./bin/maing++, opening a terminal in the bin folder and entering ./maing++ doesn't work, and so does running the .exe file manually, what did I do wrong? what I want is all the .o files made in obj/ and to be able to run the executable manually
UPDATE:
I changed the makefile to
CC = g++
CFLAGS = -std=c++2b -Wno-parentheses -Iinclude/ -Idoc/
SOURCES := $(wildcard src/*.cpp)
OBJECTS := $(patsubst src/%.cpp, obj/%.o, $(SOURCES))
All: build
obj/%.o: src/%.cpp
$(CC) $(CFLAGS) -c $< -o $#
build: $(OBJECTS)
$(CC) $(CFLAGS) $^ -o bin/is$(compiler)
this will put all obj files in the correct folder, its a simple program so running the executable would pop up a terminal window and print some text, I'm going to reiterate that I had to specifically open a terminal in the main directory and enter ./bin/maing++, opening a terminal in the bin folder and entering ./maing++ doesn't work, and so does running the .exe file manually