Creating a 4 State Mealy Finite State Machine using Verilog [HELP] - state
I'm trying to figure out how to get this to run without getting any errors.
module main;
(
input wire clk, reset;
input wire x, y;
output reg n, c;
s0 = 0,
s1 = 1,
s2 = 2,
s3 = 3;
state_reg;
state_next;
);
always(posedge clk, posedge reset)
begin
if (reset) begin
state_reg = s0;
end
else begin
state_reg = state_next;
end
end
always (x, y, state_reg) begin
state_next = state_reg;
n = 0;
c = 0;
case (state_reg)
s0 : begin
if (x == 0 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x == 0 && y == 1) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 1) begin
n = 1;
c = 0;
state_next = s1;
end
end
s1 : begin
if (x == 0 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x == 0 && y == 1) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 1) begin
n = 1;
c = 0;
state_next = s2;
end
end
s2 : begin
if (x == 0 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x == 0 && y == 1) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 1) begin
n = 1;
c = 1;
state_next = s3;
end
end
s3 : begin
if (x == 0 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x == 0 && y == 1) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 0) begin
n = 0;
c = 1;
state_next = s3;
end
else if (x== 1 && y == 1) begin
n = 1;
c = 1;
state_next = s3;
end
end
endcase
endmodule
I feel like the code enough should show what I'm trying to do but in case it doesn't I've also attached an image of the logic schematic version (I'm not sure how to attach the .cct file of the schematic on this website due to me being new). Sorry guys this is somewhat my first time using Verilog so I'm really new to this but I have to write this for an honors project with zero guidance. So the output should be if I input x or y with either 0 or 1, it should switch to a different state depending on the conditions (s0, s1, s2, s3) etc. If I hit reset, it should go back to s0, if I hit clk or the clock variable, it should take the inputs x and y to decide what the next state should be.
EDIT: Here are the errors I'm getting.
jdoodle.v:2: syntax error
jdoodle.v:3: error: invalid module item.
jdoodle.v:6: syntax error
jdoodle.v:6: error: Invalid module instantiation
jdoodle.v:11: error: Invalid module instantiation
jdoodle.v:12: error: Invalid module instantiation
jdoodle.v:13: error: invalid module item.
jdoodle.v:14: syntax error
jdoodle.v:17: Syntax in assignment statement l-value.
jdoodle.v:18: syntax error
jdoodle.v:20: error: invalid module item.
jdoodle.v:21: syntax error
jdoodle.v:25: error: invalid module item.
jdoodle.v:26: syntax error
jdoodle.v:26: error: Invalid module instantiation
jdoodle.v:27: error: Invalid module instantiation
jdoodle.v:31: syntax error
jdoodle.v:31: error: Invalid module instantiation
jdoodle.v:32: error: Invalid module instantiation
jdoodle.v:33: error: Invalid module instantiation
jdoodle.v:36: syntax error
jdoodle.v:36: error: Invalid module instantiation
jdoodle.v:37: error: Invalid module instantiation
jdoodle.v:38: error: Invalid module instantiation
jdoodle.v:41: syntax error
jdoodle.v:41: error: Invalid module instantiation
jdoodle.v:42: error: Invalid module instantiation
jdoodle.v:43: error: Invalid module instantiation
jdoodle.v:46: syntax error
jdoodle.v:46: error: Invalid module instantiation
jdoodle.v:47: error: Invalid module instantiation
jdoodle.v:48: error: Invalid module instantiation
jdoodle.v:53: syntax error
jdoodle.v:53: error: Invalid module instantiation
jdoodle.v:54: error: Invalid module instantiation
jdoodle.v:55: error: Invalid module instantiation
jdoodle.v:58: syntax error
jdoodle.v:58: error: Invalid module instantiation
jdoodle.v:59: error: Invalid module instantiation
jdoodle.v:60: error: Invalid module instantiation
jdoodle.v:63: syntax error
jdoodle.v:63: error: Invalid module instantiation
jdoodle.v:64: error: Invalid module instantiation
jdoodle.v:65: error: Invalid module instantiation
jdoodle.v:68: syntax error
jdoodle.v:68: error: Invalid module instantiation
jdoodle.v:69: error: Invalid module instantiation
jdoodle.v:70: error: Invalid module instantiation
jdoodle.v:75: syntax error
jdoodle.v:75: error: Invalid module instantiation
jdoodle.v:76: error: Invalid module instantiation
jdoodle.v:77: error: Invalid module instantiation
jdoodle.v:80: syntax error
jdoodle.v:80: error: Invalid module instantiation
jdoodle.v:81: error: Invalid module instantiation
jdoodle.v:82: error: Invalid module instantiation
jdoodle.v:85: syntax error
jdoodle.v:85: error: Invalid module instantiation
jdoodle.v:86: error: Invalid module instantiation
jdoodle.v:87: error: Invalid module instantiation
jdoodle.v:90: syntax error
jdoodle.v:90: error: Invalid module instantiation
jdoodle.v:91: error: Invalid module instantiation
jdoodle.v:92: error: Invalid module instantiation
jdoodle.v:97: syntax error
jdoodle.v:97: error: Invalid module instantiation
jdoodle.v:98: error: Invalid module instantiation
jdoodle.v:99: error: Invalid module instantiation
jdoodle.v:102: syntax error
jdoodle.v:102: error: Invalid module instantiation
jdoodle.v:103: error: Invalid module instantiation
jdoodle.v:104: error: Invalid module instantiation
jdoodle.v:107: syntax error
jdoodle.v:107: error: Invalid module instantiation
jdoodle.v:108: error: Invalid module instantiation
jdoodle.v:109: error: Invalid module instantiation
jdoodle.v:112: syntax error
jdoodle.v:112: error: Invalid module instantiation
jdoodle.v:113: error: Invalid module instantiation
jdoodle.v:114: error: Invalid module instantiation
There are several syntax errors preventing this module from compiling.
The semicolon after the module name 'main' is a syntax error.
Semicolons in the IO list (after the module name are errors, need to be commas.
You are tying to declare a state variables is the IO list area (just after the word module . Its an error. Put the declarations after IO listing.
Search 'verilog state machine' to learn how and where to declare the state variables.
You need non-blocking assignments (<=) rather than non blocking assignments (=) in the always block with the clock.
Your always blocks were missing the timing control operator #.
You were missing a 'end' keyword at the end of the module.
The state machine does not have a :default state, which could cause some strange behavior.
I made these changes (did not add a :default state because it will modify your design intent).
Here is your code that now compiles using Mentor Questa on edaplayground.com
You did not post a testbench, there is no way to know if it behaves the way you want it to or not.
Search on 'basic verilog testbench' to get started on a testbench design.
module main
(
input wire clk,
input wire reset,
input wire x,
input wire y,
output reg n,
output reg c
);
localparam
s0 = 2'b00,
s1 = 2'b01,
s2 = 2'b10,
s3 = 2'b11;
reg [1:0] state_reg,state_next;
always #(posedge clk, posedge reset)
begin
if (reset) begin
state_reg <= s0;
end
else begin
state_reg <= state_next;
end
end
always #(x, y, state_reg) begin
state_next = state_reg;
n = 0;
c = 0;
case (state_reg)
s0 : begin
if (x == 0 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x == 0 && y == 1) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 1) begin
n = 1;
c = 0;
state_next = s1;
end
end
s1 : begin
if (x == 0 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x == 0 && y == 1) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 1) begin
n = 1;
c = 0;
state_next = s2;
end
end
s2 : begin
if (x == 0 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x == 0 && y == 1) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 1) begin
n = 1;
c = 1;
state_next = s3;
end
end
s3 : begin
if (x == 0 && y == 0) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x == 0 && y == 1) begin
n = 0;
c = 0;
state_next = s0;
end
else if (x== 1 && y == 0) begin
n = 0;
c = 1;
state_next = s3;
end
else if (x== 1 && y == 1) begin
n = 1;
c = 1;
state_next = s3;
end
end
endcase
end
endmodule
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