Makfile usees same cpp file to generate objects [duplicate] - c++

This is a part of my makefile :
SRC = ./
DIRS = src libs/maths libs/struct
BIN_DIR = ./bin/
SRC_DIRS= $(foreach dir, $(DIRS), $(addprefix $(SRC), $(dir)))
SRC_TEST= $(sort $(SRC_DIRS))
SRCS = $(foreach msrc, $(SRC_DIRS), $(wildcard $(msrc)/*.c))
DEL_PRE = $(foreach target, $(SRCS), $(notdir $(target)))
ADD_PRE = $(foreach target, $(DEL_PRE), $(addprefix $(BIN_DIR), $(target)))
OBJS = $(ADD_PRE:.c=.o)
.PHONY: all clean re
all: $(EXEC)
$(EXEC): $(OBJS)
$(CC) $(OBJS) -o $# $(LDLIBS)
$(OBJS): $(SRCS)
$(CC) -o $# -c $<
When i use make all, i have in output :
gcc -o bin/main.o -c src/main.c
gcc -o bin/cosin.o -c src/main.c
gcc -o bin/pears.o -c src/main.c
gcc -o bin/outil.o -c src/main.c
gcc -o bin/verif.o -c src/main.c
But i would like to have for each target, it assigned dependency :
gcc -o bin/main.o -c src/main.c
gcc -o bin/cosin.o -c libs/maths/cosin.c
gcc -o bin/pears.o -c libs/maths/pears.c
gcc -o bin/outil.o -c libs/struct/outil.c
gcc -o bin/verif.o -c libs/struct/verif.c
How can i fix it ?

This seems like a very common misconception; I just answered effectively this same question yesterday. I'm not sure where it comes from or how to combat it.
This rule:
$(OBJS): $(SRCS)
$(CC) -o $# -c $<
does not somehow magically combine the contents of the OBJS variable and the SRCS variable to figure out how they match up. The variable references are simply expanded, and the result is this:
bin/main.o bin/cosin.o ... : src/main.c libs/maths/cosin.c ...
$(CC) -o $# -c $<
which is the same as if you'd written this:
bin/main.o : src/main.c libs/maths/cosin.c ...
$(CC) -o $# -c $<
bin/cosin.o : src/main.c libs/maths/cosin.c ...
$(CC) -o $# -c $<
...
Now, you can hopefully see why you compile the same file: in every rule you have the same prerequisites, so $< is always the first one, which is always src/main.c.
There are multiple ways to work this but if you really want to have all the source files from different directories compiled into object files in the same directory your job is harder, because there's no common pattern that will match them all. In this case the simplest thing to do is use VPATH for directory search: replace the above rule with this:
$(BIN_DIR)/%.o : %.c
$(CC) -o $# -c $<
then tell make how to find your source files, like this:
VPATH := $(sort $(dir $(SRCS))
Be aware this method can't be used for any source files that are themselves generated output that make is expected to create.

Related

What is the diferrence between $(objs): %.o : %.cpp and $(objs): $(objs:.o=.cpp) in Makefile

I have add.c sub.c in current directory and compile them through makefile.
I do the following:
program 1:
objs=$(patsubst %.cpp, %.o, $(wildcard *.cpp))
$(objs): %.o : %.cpp
g++ -o $# -c $<
program 2:
objs=$(patsubst %.cpp, %.o, $(wildcard *.cpp))
$(objs): $(objs:.o=.cpp)
g++ -o $# -c $<
Program 1 compiles successfully. But program 2 gets the following command:
g++ -o sub.o -c sub.cpp
g++ -o add.o -c sub.cpp
So what's the diferrence between these two programs?
The rule in makefile 1 is equivalent to
sub.o: sub.cpp
g++ -o $# -c $<
add.o: add.cpp
g++ -o $# -c $<
which works correctly.
The rule in makefile 2 expands to
sub.o add.o: sub.cpp add.cpp
g++ -o $# -c $<
Which says that each of those two targets depends on both source files. Note that the automatic variable $< expands to the first prerequisite, which in this case is sub.cpp. So that's the only source file that the rule uses, even when attempting to build add.o.

Makefile not updating one particular file

I have a makefile which works fine for all other files, but not for the main.cpp file. When I change the main.cpp file, it does not update main.o.
here is the makefile:
CXX = g++
SRCF = main.cpp Animal.cpp
SRC = $(addprefix src/, $(SRCF))
VER = Debug
CXXFLAGS = -Wall -std=c++17
EXE = Animal
OBJF = $(subst .cpp,.o, $(SRCF))
OBJ = $(addprefix src/obj/, $(OBJF) )
#PKG = `pkg-config --libs --cflags sdl2`
$(VER)/$(EXE) : $(OBJ)
$(CXX) $(CXXFLGS) -o $# $< $(PKG)
src/obj/%.o:src/%.cpp src/%.h
$(CXX) $(CXXFLGS) -c -o $# $< $(PKG)
clean:
rm -rf $(EXE) $(OBJ)
print-% : ; #echo $* = $($*)
When I change Animal.h or Animal.cpp it updates Animals.o and the Animal executable. But why does it not work for main ?? I have specified how to update main.o in this line :-
src/obj/%.o:src/%.cpp src/%.h
$(CXX) $(CXXFLGS) -c -o $# $< $(PKG)
Please help me and thanks it advance :)
In the Introduction to Pattern Rules section of GNU Make's manual:
In order for the pattern rule to apply, its target pattern must match the file name under consideration and all of its prerequisites (after pattern substitution) must name files that exist or can be made.
Therefore, if there is no src/main.h (or can't be made), the following pattern rule will not match against src/obj/main.o:
src/obj/%.o: src/%.cpp src/%.h
$(CXX) $(CXXFLGS) -c -o $# $< $(PKG)
You need an additional pattern rule without the src/%.h prerequisite:
src/obj/%.o: src/%.cpp
$(CXX) $(CXXFLGS) -c -o $# $< $(PKG)

Make recompiles non modified files

I have a makefile for my program but I got everything recompiled every time I run it, even if I modify nothing.
Every time I run make it recompiles simHwIntf.cpp showHelp.cpp and sendFromFile.cpp
This is my make file:
IDIR = inc
LDIR = -L/usr/lib/x86_64-linux-gnu/
SDIR = src
ODIR = obj
BINDIR = bin
LDLIBS = -luhd
OBJ = $(patsubst %,$(ODIR)/%,$(O_FILES))
CC = g++
CFLAGS = -Wall -std=c++11 -I $(IDIR) #-Werror
BINARIES= main
C_FILES = simHwIntf.cpp showHelp.cpp sendFromFile.cpp
H_FILES = simHwIntf.h
O_FILES = $(C_FILES:.cpp=.o)
all: $(BINARIES)
#echo "Make file executed"
$(BINARIES): $(O_FILES)
$(CC) $(CFLAGS) -o $(BINDIR)/$# $(OBJ) $(LDIR) $(LDLIBS)
fileCreator: fileCreator.o
$(CC) $(CFLAGS) -o $(BINDIR)/$# $(ODIR)/fileCreator.o
fileHandler: fileHandler.o
$(CC) $(CFLAGS) -o $(BINDIR)/$# $(ODIR)/fileHandler.o
backYard: backYard.o
$(CC) $(CFLAGS) -o $(BINDIR)/$# $(ODIR)/backYard.o
%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
$(CC) $(CFLAGS) -c -o $(ODIR)/$# $<
clean:
-rm -rf $(ODIR)/*.o *~
distclean: clean
-rm -rf $(BINDIR)/*
Each time the output in the shell is:
g++ -Wall -std=c++11 -I inc -c -o obj/simHwIntf.o src/simHwIntf.cpp
g++ -Wall -std=c++11 -I inc -c -o obj/showHelp.o src/showHelp.cpp
g++ -Wall -std=c++11 -I inc -c -o obj/sendFromFile.o src/sendFromFile.cpp
g++ -Wall -std=c++11 -I inc -o bin/main obj/simHwIntf.o obj/showHelp.o obj/sendFromFile.o -L/usr/lib/x86_64-linux-gnu/ -luhd
Make file executed
I've already search and read this: (How do I make Makefile to recompile only changed files?) but didn't help much.
Anybody that could give me a hand with this ?
I have a doubt with the directories, maybe one or several directories are re-created each time I run make and this causes everything inside to look like new to the compiler.
Thanks
You can see what triggered the build by echoing the dependencies that changed. Add this to your %.o target :
#echo [triggered by changes in $?]
You should also use the VPATH special variable instead of specifying the sources path in your %.o target. See GNU make VPATH documentation
Please try replacing
%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
$(CC) $(CFLAGS) -c -o $(ODIR)/$# $<
with
$(ODIR)/%.o: $(SDIR)/%.cpp $(IDIR)/$(H_FILES)
$(CC) $(CFLAGS) -c -o $(ODIR)/$# $<
Directories matter when you define targets.
If a define a rule
myexec: objdir/myexec.o
$(CC) $(CFLAGS) -o bindir/myexec objdir/myexec.o $(LDFLAGS)
Make believes that that this would create the file myexec in the working directory. When you rerun make the target myexec wasn't found, so it will be created again. Add the paths in the targets and it should work.
Try replacing
BINARIES= main
with
BINARIES= $(BINDIR)/main
and the rule
$(CC) $(CFLAGS) -o $(BINDIR)/$# $(OBJ) $(LDIR) $(LDLIBS)
with
$(CC) $(CFLAGS) -o $# $^ $(LDIR) $(LDLIBS)
And change the other rules similarly.
Note, in general it is a bad idea to use $# in combination with a path when creating the target in some rule (as in $(BINDIR)/$#), because this will never create the actual target file. A bare $# should be sufficient.

make objects in Makefile

I have the following Makefile:
CXX = g++
CXXFLAGS = -Wall -g
SOURCES := divisor.cpp multiplier.cpp
OBJECTS := ${SOURCES:.cpp=.o}
%.o: %.cpp
$(CXX) -c $(CXXFLAGS) $< -o $#
%: %.o $(OBJECTS)
$(CXX) $(CXXFLAGS) $#.o -o $#.out
$(OBJECTS): %.o: %.cpp
$(CXX) -c $(CXXFLAGS) $< -o $#
clean:
rm -f *.o
What I want this make file is the following:
If I add a source file called 123.cpp to the working directory, I want it to generate its object file and then link the compiled sources specified in $(SOURCES), this means:
g++ -c -Wall -g 123.cpp
g++ multipler.o divisor.o 123.o -o 123
If multiplier.cpp or divisor.cpp has to be generated or updated, I want make to do it.
But I'm failing, because divisor.o and multiplier.o are not automatically generated
How may I achieve this?
Edit
Just to clarify, there are two types of source code files in the working directory: divisor.cpp, multipler.cpp is one type, and any other file, say, 123.cpp is the other type. In a sense, divisor.cpp and multiplier.cpp are requisites to the other source files.
I want to automate the process of compiling the prerequisites and link them when compiling the other files
g++ -c multiplier.cpp
g++ -c divisor.cpp
g++ -c -Wall -g 123.cpp
g++ multipler.o divisor.o 123.o -o 123
Use the wildcard function:
SOURCES := $(wildcard *.cpp)
Then, you can remove your "special" source files:
SPECIAL_SOURCES := divisor.cpp multiplier.cpp
SOURCES := $(filter-out $(SPECIAL_SOURCES),$(SOURCES))
And change your rules to build the stuff you actually want:
$(SPECIAL_OBJECTS) := $(SPECIAL_SOURCES:.cpp=.o)
$(BINARIES) := $(patsubst .cpp,,$(SOURCES))
$(SPECIAL_OBJECTS) : %.o : %.cpp
$(CXX) $(CXXFLAGS) -c -o $# $^
$(BINARIES) : % : %.cpp $(SPECIAL_OBJECTS)
$(CXX) $(CXXFLAGS) -o $# $^

Refactoring Makefile for object files with different flags

I have some source .cpp files in the same directory, and I want to compile them as object file.
Some of them needs "extra" libraries (same libs for all files) to be linked with and some of them don't, I'd like to write general rules to match the right files, without writing specific rule for each file with extra flags.
More in detail I want to refactor my Makefile so that I don't have to specify different rules for the source files SourceFileOpenCVNeeded.cpp OCVAlsoHere.cpp TheSameForMe.cpp (now they're few, but they could be many more).
Here is what my makefile actually looks like:
CPP_FILES := $(wildcard src/*.cpp)
OBJ_FILES := $(addprefix obj/,$(notdir $(CPP_FILES:.cpp=.o)))
MAIN_SRC := main.cpp
OCV_LIBS := `pkg-config opencv --libs`
OCV_PATH := `pkg-config opencv --cflags`
MY_LIB := launcher
LD_FLAGS := $(MAIN_SRC) -L. -l$(MY_LIB) $(OCV_LIBS)
CC_FLAGS := -c -fPIC
AR_FLAGS := rcs
STATIC_LIB := lib$(MY_LIB).a
CC := g++
EXEC := test
all: lib main
main:
$(CC) $(LD_FLAGS) -o $(EXEC)
lib: $(OBJ_FILES)
ar $(AR_FLAGS) $(STATIC_LIB) $^
obj/SourceFileOpenCVNeeded.o: src/SourceFileOpenCVNeeded.cpp
$(CC) $(OCV_PATH) $(CC_FLAGS) $(OCV_LIBS) -c -o $# $<
obj/OCVAlsoHere.o: src/OCVAlsoHere.cpp
$(CC) $(OCV_PATH) $(CC_FLAGS) $(OCV_LIBS) -c -o $# $<
obj/TheSameForMe.o: src/TheSameForMe.cpp
$(CC) $(OCV_PATH) $(CC_FLAGS) $(OCV_LIBS) -c -o $# $<
obj/%.o: src/%.cpp
$(CC) $(CC_FLAGS) -c -o $# $<
clean:
rm -f $(OBJ_FILES) $(STATIC_LIB) $(EXEC)
PS: any other improvements that can be added to my Makefile?
You might be able to use target-specific variables, e.g. (not tested)
EXTRA_FLAGS=
obj/TheSameForMe.o: EXTRA_FLAGS="$(OCV_PATH) $(OCV_LIBS)"
obj/%.o: src/%.cpp
$(CC) $(CC_FLAGS) $(EXTRA_FLAGS) -c -o $# $<