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I have a general question about state machines used in VHDL. I heard that every state is processed in one clock cycle.
So lets say I have a state that needs more than one clock cycle to be finished. For example if I want to wait for a few seconds inside a state. Can this be done?
Or if I have a state in which I want to write to a blockram which needs 10 clock cycles (10 adresses) to be filled. Can this be done inside the case statements which are typically used for presenting state machines?
Usually in cases when you need to execute N repetitive actions in one state (like you described, waiting N ns, writting to N addresses.) it is often used a counter in it. Hope the following example may clarify it a bit:
process(clk, rst)
begin
if (rst = '1') then
index <= 0; -- memory address
current_s <= write_memory ;
currentValue <= (others => '0');
elsif rising_edge(clk) then
case curresnt_s is
when write_memory =>
if index < ADDRESS_SIZE then
index <= index + 1;
memory(index) <= currentValue;
else
curresnt_s <= done;
end if;
when done => null;
end case;
end case;
In this code memory would be an array of std_logic_vector;
You could use the same idea to wait for 100ns.
if you know your clock runs at 10ns period, you could count to 10 in some state before changing to other.
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Consider the following pseudo code:
Pseudocode:
list_Sum(A,n){//A->array and n->number of elements in the array
sum =0 // cost=1 no of times=1
for i=0 to n-1 // cost=2 no of times=n+1 (+1 for the end false condition)
sum = sum + A[i] // cost=2 no of times=n
return sum // cost=1 no of times=1
}
What does cost mean in context of time complexity?
Nothing, actually. Theoretically, this would be the number of instructions required on a fictional architecture made up by the author. Practically, it doesn't map to any existing, relevant architecture. No real architecture has exactly these costs.
The only relevant part is the times 1 or times n part, as that is applicable regardless of architecture.
There is also vectorization and super-scalarity, which easily slice the cost of e.g. the loop by factor 15-50 (so imagine that as a "real" cost of 0.02 for the body of the loop), but even then it stays times n.
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I recently came across Verilog code of this structure:
reg flop_a;
always #(posedge clk) begin
if (reset)
flop_a <= 1'b0;
else if (some_condition)
flop_a <= new_value;
end
I would have explicitly coded a register's hold path, but leaving out the "else" condition and implying the hold path seems to work as well.
Why does this (safely) work? I can't find anything in the verilog IEEE spec's definition of an always block or if statement that defines this behavior.
If there is no else branch, when none of the conditions are met, flop_a will not be affected by the always block, hence it will keep its old value.
This is exactly the same behavior if you add the else branch with flop_a <= flop_a;
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I am developing the optimization of a bus schedule problem in c++ and need to code each of the constraints, however I am struggling to know how to code a particular kind of constraint.
The sets i,j,k and h all range from 1 to I,J,K and H respectively. My confusion lies with how to code the left hand side of the constraint. I am trying to use for loops however I am getting confused as to how to implement the for all i,h part.
My question is how to code the left hand side of the equation, given that X is a four dimensional array. I so far have two for loops, looping from j,k = 0 to j,k < J,K. How would I include for all i,h
Any help would be greatly appreciated =)
In pseudo code that would be
for all i
for all h
sum = 0
for all j
for all k
sum += X[i,h,j,k]
if (sum != 1) -> condition not satisfied
You basically have for each combination of i and h a seperate condition that has to be satisfied. For each of those conditions you have to sum over j and k.
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I have to generate & publish data (as protocol buffer messages) with a frequency of 1Hz and I have been thinking of alternatives to just sticking it into a While loop with a clock() function. Maybe I am over thinking the issue but any advice on the matter would be much appreciated thanks
There are many ways to call a function on a regular interval. Which one is best depends on the situation and needs of the program. There's no single "best way".
A few possibilities (there are many more):
Sit in a loop and sleep for some duration every time round the loop. Simple, easy to understand. But rarely the best solution, since nothing else can happen while you sleep.
Sit in a loop waiting for some event to occur. Like a timer event. Process each event as it arrives - if not enough time has passed, ignore the event (maybe).
Set up a timer with a callback function that will call the function at regular intervals.
If your intervals are very tiny, then maybe spin / busy-wait in a loop and check elapsed time each time around the loop and do something when enough time has passed (rarely a good idea since it will burn a lot of CPU time doing nothing, but sometimes it's the right option).
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I know how to do this and have made a program that does so in the past, however it never incorporated the special cases of roman numerals (e.g. IV = 4). Integrating that into a functional program in a minimalistic way is my main problem. Is there a good way to do this?
A very simple solution, in pseudo-code, could look something like this:
value = get_the_value_to_convert();
divider = 1000; // Start at 1000 (M)
while (value > 0)
{
count = value / divider;
value = value % divider;
for (i = 0; i < count; ++i)
print(roman_numeral_from_number(divider));
divider /= 10;
}
The roman_numeral_from_numbe function does a one-to-one mapping between a number and a roman numeral.
For e.g. 5432 as input it would print MMMMMCCCCXXXII.
For better results, divide the divider variable with 2 and 5 every second time.
For even better results, add check for certain numbers, like 90 being equal to "XC".
Note that even with the modifications, the above algorithm can't handle very large numbers, but on the other hand Wikipedia states that historically it was only used for small numbers anyway.