What's the difference between IRBuilderBase and BinaryOperator in LLVM API ?
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I read that llvm is backend having multiple frontend, c, c++, swift ...
So, can I convert ir code based something to ir code based another?
Or, can I just use ir code in different language project?
How do I generate a while loop using the llvm c++ api. I would like to understand how the branching and phi instructions work together
I'm just starting to get acquainted with LLVM and I have been looking for information regarding the actual state of LLVM's JIT API and implentation. A lot of examples I had found, show usage either of ExecutionEngine class or MCJit/ORC API, but never show them in conjunction.
Therefore my question is: what exactly is the relation between ExecutionEngine class and MCJit/ORC API? Currently, my understanding is that ExecutionEngine is a kind of API class for both MCJit and ORC, hiding their implementation details. Is this correct? Can it be assumed that one should always use ExecutionEngine class instead of MCJit/ORC API? If so, why official LLVM's tutorial uses ORC API directly and doesn't even mention the existence of ExecutionEngine class? Is it just outdated?
As far as I have understood, LLVM doesn't let you enforce using a specific processor register. Does that mean a language that uses LLVM under the hood, can't be used for developing an OS, a bootloader or such things that for example requires direct access to registers?
Are there any other reasons why LLVM IR can or cannot be used in OS development?
LLVM is an abstract machine. As such, it does not directly allow you to access certain hardware registers. However, you can still use inline assembly (through the call asm LLVM bitcode mnemonic) or program the few functions that need access to fixed hardware registers in assembly and call them from your LLVM code.
Is there a machanism to convert native machine code to llvm bytecode?
If not, please give some idea how to implement it.
Thanks!
Libcpu was designed to convert machine code of various architectures to LLVM IR to facilitate writing emulators.