Manipulate a clocked signal in order to get 10 pulses - if-statement

Question

I am attempting to create a very specific signal in my code. Basically I need a signal to be generated after load_0 ends, in the falling edge, where such signal would be 10 pulses of the 1KHz signal and the rest 0. Which is just preserving 10 pulses that are aligned with the variable Serial_out.
Thus far I have tried an if to attempt this, with a counter to attempt to count to 10 for the 10 pulses i want and discarding the rest. This always ends either not being able to be synthesized due to error or the test bench clk_trig never being initialized.
My coding is quite crude due to the fact that I have not been using xilinx for long.
Main section of the code
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HAMMING IS
PORT ( CLK_50MHz_M : IN STD_LOGIC;
RST : IN STD_LOGIC;
LOAD_O : IN STD_LOGIC;
input1 : IN STD_LOGIC;
input2 : IN STD_LOGIC;
input3 : IN STD_LOGIC;
input4 : IN STD_LOGIC;
input5 : IN STD_LOGIC;
input6 : IN STD_LOGIC;
CLK_DIV_O : OUT STD_LOGIC;
CLK_TRIG : OUT STD_LOGIC;
Serial_out : OUT STD_LOGIC);
END HAMMING;
ARCHITECTURE ARCH OF HAMMING IS
SIGNAL input_vec : STD_LOGIC_VECTOR(6 DOWNTO 1);
SIGNAL output : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL CLK_100Hz, CLK_50KHz : STD_LOGIC;
COMPONENT P2S
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(9 downto 0);
dout : out STD_LOGIC);
END COMPONENT;
COMPONENT SCALE_CLOCK
PORT (CLK_50MHz_S : IN STD_LOGIC;
RST : IN STD_LOGIC;
CLK_100Hz : OUT STD_LOGIC);
END COMPONENT;
begin
----------------------------------------------
process (LOAD_O, CLK_100Hz)
begin
if (LOAD_O = '1') then CLK_TRIG <= '0'; -crude attempt at the desired signal
ELSE
CLK_TRIG <= CLK_100Hz;
end if;
end process;
---------------------------------------------
-- BITS DE PALABRA
output(2) <= input_vec(1);
output(4) <= input_vec(2);
output(5) <= input_vec(3);
output(6) <= input_vec(4);
output(8) <= input_vec(5);
output(9) <= input_vec(6);
-- BIT PARIEDAD
output(0) <= input_vec(1) XOR input_vec(2) XOR input_vec(4) XOR input_vec(5);
output(1) <= input_vec(1) XOR input_vec(3) XOR input_vec(4) XOR input_vec(6);
output(3) <= input_vec(2) XOR input_vec(3) XOR input_vec(4);
output(7) <= input_vec(5) XOR input_vec(6);
ClockDiv: SCALE_CLOCK PORT MAP(CLK_50MHz_S => CLK_50MHz_M, RST => RST, CLK_100Hz => CLK_100Hz);
SeriesOut: P2S PORT MAP(clk => CLK_100Hz, din => output, dout => Serial_out, reset => RST, load => LOAD_O);
CLK_DIV_O <= CLK_100Hz;
input_vec <= input1 & input2 & input3 & input4 & input5 & input6;
END ARCH;
FPGA2 code running

Answer 1

You have a 50MHz clock.
from that you probably decided to make a nice 50/50 100Hz clock and then use that.
That is the wrong strategy!
You always want as much as possible a synchronous design.
If you want signals to change at 100Hz the right (synchronous) method is as follows:
Make 100Hz pulses which are high for one 50MHz clock only. (e.g. P100Hz)
Everywhere you use a 100Hz clock go back to using the 50 MHz clock
then in the 50MHz clock section use an additional if P100Hz then
You now have a synchronous design running at effectively 100Hz.