I'm programming on Xcode. I include SDL_image.h as
#include <SDL2/SDL_image.h>
and it says 'SDL2/SDL_image.h' file not found
I have installed and linked binary with libraries both SDL2.framework and SDL2_image.framework.
I used a Makefile to compile and there is an error: fatal error: 'SDL2/SDL_image.h' file not found
Here is my Makefile
# set the compiler
CC := clang
# set the compiler flags
CXXFLAGS = -std=c++14 -Wall -MMD -Werror=vla pkg-config --cflags --libs sdl2 `-L/Library/Frameworks/ sdl2-config --libs --cflags` -ggdb3 -O0 --std=c99 -Wall -l SDL2_image -lm
# add source files here
SRCS := main.cpp #file-name.c
# generate names of object files
OBJS := $(SRCS:.c=.o)
# name of executable
EXEC := sdl #name your executable file
# default recipe
all: $(EXEC)
showfont: showfont.c Makefile
$(CC) -o $# $#.c $(CFLAGS) $(LIBS)
glfont: glfont.c Makefile
$(CC) -o $# $#.c $(CFLAGS) $(LIBS)
# recipe for building the final executable
$(EXEC): $(OBJS) $(HDRS) Makefile
$(CC) -o $# $(OBJS) $(CFLAGS)
# recipe for building object files
#$(OBJS): $(#:.o=.c) $(HDRS) Makefile
# $(CC) -o $# $(#:.o=.c) -c $(CFLAGS)
# recipe to clean the workspace
clean:
rm -f $(EXEC) $(OBJS)
.PHONY: all clean
Related
When I make the Makefile everything works fine, I get a library in the directory dir. And when I run "Make test" I get a testfile that I want to run. But when I want to run this file I get this weird error: ./programma: error while loading shared libraries: libprogramma.so: cannot open shared object file: No such file or directory. I have tried running the program on both WSL and Linux, but nothing makes this error go away. Can anyone help me?
Here I have my Makefile which makes the library and the executable:
INC_DIR = include
SRC_DIR = src
SOURCES = $(sort $(shell find $(SRC_DIR) -name '*.cc'))
OBJECTS = $(SOURCES:.cc=.o)
DEPS = $(OBJECTS:.o=.d)
TARGET = programma
CXX = g++
CFLAGS = -Wall -Wextra -Wpedantic -std=c++11
CPPFLAGS = $(addprefix -I, $(INC_DIR))
.PHONY: all clean debug release
release: CFLAGS += -O3 -DNDEBUG
release: all
debug: CFLAGS += -O0 -DDEBUG -ggdb3
debug: all
all: $(TARGET)
clean:
rm -f $(OBJECTS) $(DEPS) lib/*.so programma *.d
$(TARGET): $(OBJECTS)
$(CXX) $(CFLAGS) $(CPPFLAGS) -fPIC -shared -o lib/lib$#.so $^
-include $(DEPS)
%.o: %.cc
$(CXX) $(CFLAGS) $(CPPFLAGS) -fPIC -MMD -o $# -c $<
test:
$(CXX) $(CFLAGS) -L./lib $(CPPFLAGS) -MMD -o programma tests/main.cc -l$(TARGET)
Executables on Linux don't look for shared libraries in the directory they're located in, at least by default.
You can either fix that at link-time, by passing -Wl,-rpath='$ORIGIN', or at runtime, by setting LD_LIBRARY_PATH env variable to the directory with the library. (LD_LIBRARY_PATH=path/to/lib ./programma)
I am trying to build a Makefile that will build a shared library with g++ and I find that it is not evaluating the OBJECTS variable. This is on Ubuntu 18.04 and all the files are in the same current directory. Secondly it is completely skipping the source file compilation and proceeding directly to evaluate the linking instruction. As a clarification I am using GNU Make 4.1
Here is what I get when I type make all
g++ -shared -pthread -o tree.so
g++: fatal error: no input files
compilation terminated.
Makefile:12: recipe for target 'tree.so' failed
make: *** [tree.so] Error 1
Here is my Makefile code
CC=g++
CFLAGS = -I/usr/local/include -Wall -std=c++17 -O3 -march=native -Ofast -ftree-vectorize
LIBS=-shared -pthread
SOURCES=$(wildcard *.cpp)
OBJECTS=$(wildcard *.o)
TARGET=tree.so
all:$(TARGET)
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(OBJECTS) $(TARGET)
$(OBJECTS):$(SOURCES)
$(CC) -c -g $(CFLAGS) $(SOURCES)
clean:
rm -f $(OBJECTS) $(TARGET)
If you only have the *.cpp files in your directories, then there is not any *.o yet, so your $(wildcard *.o) will expand to nothing.
What you want is to get the *.cpp files and compute the corresponding *.o files:
OBJECTS=$(patsubst %.cpp,%.o,$(SOURCES))
or equivalently:
OBJECTS=$(SOURCES:.cpp=.o)
Now, your compiler command is not the best one, because if you touch any source file all will be compiled. You can use instead:
$(OBJECTS): %.o: %.cpp
$(CC) -c -g $(CFLAGS) $< -o $#
So that only the touched files are actually rebuilt.
Also you have the linking command wrong. It should be:
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(TARGET) $(OBJECTS)
because the argument to the -o option is the output file, that is the target.
Make file:
INCLUDE = -I/usr/X11R6/include/
LIBDIR = -L/usr/X11R6/lib
COMPILERFLAGS = -Wall
CC = g++
CFLAGS = $(COMPILERFLAGS) $(INCLUDE)
LIBRARIES = -lX11 -lXi -lXmu -lglut -lGL -lGLU -lm
All: project
project: main.o landscape.o point.o
$(CC) $(CFLAGS) -o $# $(LIBDIR) $< $(LIBRARIES)
clean:
rm *.o
I have a landscape.cpp, landscape.h, point.cpp, point.h, and main.cpp files
I'm including "point.h" in my main.cpp file and i'm getting:
g++ -Wall -I/usr/X11R6/include/ -o project -L/usr/X11R6/lib main.cpp -lX11 -lXi -lXmu -lglut -lGL -lGLU -lm
/tmp/ccdpJ8HH.o: In function main':
main.cpp:(.text+0x1c0): undefined reference toPoint::Point(int, int)'
collect2: error: ld returned 1 exit status
Makefile:15: recipe for target 'project' failed
make: *** [project] Error 1
project: main.o landscape.o point.o
$(CC) $(CFLAGS) -o $# $(LIBDIR) $< $(LIBRARIES)
Here you need to link all .o files. The rule you have here will only use the main.o file. Because $<is the first dependency only. $^ should be for all three. So try:
project: main.o landscape.o point.o
$(CC) $(CFLAGS) -o $# $(LIBDIR) $^ $(LIBRARIES)
I suggest you to use a more complete Makefile.
Also, use CXX=g++ and CXXFLAGS instead of CC and CFLAGS, because you are compiling C++ and make have special variables.
Here is an example of Makefile I could use.
# Project name
NAME= project
# Include directory
INC_DIR= /usr/X11R6/include/
# Library directory
LIB_DIR= /usr/X11R6/lib/
# Compiler
CXX= g++
# Source files
SRC_DIR= # in case your cpp files are in a folder like src/
SRC_FILES= main.c \
landscape.c \
point.c
# Obj files
OBJ= $($(addprefix $(SRC_DIR), $(SRC_FILES)):.c=.o)
# that rule is composed of two steps
# addprefix, which add the content of SRC_DIR in front of every
# word of SRC_FILES
# And a second rule which change every ".c" extension into ".o"
LIBS= X11 \
Xi \
Xmu \
glut \
GL \
GLU \
m
# Compilation flags
CXXFLAGS= -Wall
CXXFLAGS+= $(addprefix -I, $(INC_DIR))
LDFLAGS= $(addprefix -L, $(LIB_DIR)) \
$(addprefix -l, $(LIBS))
# Rules
# this rule is only linking, no CFLAGS required
$(NAME): $(OBJ) # this force the Makefile to create the .o files
$(CXX) -o $(NAME) $(OBJ) $(LDFLAGS)
All: $(NAME)
# Remove all obj files
clean:
rm -f $(OBJ)
# Remove all obj files and the binary
fclean: clean
rm -f $(NAME)
# Remove all and recompile
re: fclean all
# Rule to compile every .c file into .o
%.o: %.c
$(CXX) -o $# -c $< $(CFLAGS)
# Describe all the rules who do not directly create a file
.PHONY: All clean fclean re
I'm not sure it's perfect, but it's better.
Also don't forget to put you project rule before your All rule to avoid relinking when simply calling make.
That way, you can also add beautiful messages (in the %.o: %.c rule for example).
With that you just have to do make re to get your binary fully updated.
I have created a makefile for a library I am compiling.
I have already got the makefile working on windows and linux , but there is a different makefile for each OS.
How could I allow this to work on both OS without hardcoding the path to the boost library and boost headers below:
Do I need to add the boost folder to the path variable? do I need to add the library directory to some OS variable?
makefile windows:
# source files.
SRC = protoService.cpp protocolBaseServer.cpp client.cpp
OBJ = $(SRC:.cpp=.o)
OUT = ../libutils.a
# include directories
INCLUDES = -I. -I../include/ -IC:\boost_1_59_0\
# C++ compiler flags (-g -O2 -Wall)
CCFLAGS = -g -MD -MP -std=c++0x -Wall -c
# compiler
CCC = g++
# library paths
LIBS = -LC:\boost_1_59_0\libs -lboost_serialization
# compile flags
LDFLAGS = -g
.SUFFIXES: .cpp
default: $(OUT)
.cpp.o:
$(CCC) $(INCLUDES) $(CCFLAGS) $< -o $#
$(OUT): $(OBJ)
ar rcs $(OUT) $(OBJ)
#depend: dep
#dep:
# makedepend -- $(CFLAGS) -- $(INCLUDES) $(SRC)
clean:
rm -f $(OBJ) $(OUT) Makefile.bak
-include $(DEPS:%.o=%.d)
makefile linux:
# source files.
SRC = protoService.cpp protocolBaseServer.cpp client.cpp
OBJ = $(SRC:.cpp=.o)
OUT = ../libutils.a
# include directories
INCLUDES = -I. -I../include/ -I/usr/local/include -I/usr/share/boost_1_58_0/
# C++ compiler flags (-g -O2 -Wall)
CCFLAGS = -g -MD -MP -std=c++0x -Wall -c
# compiler
CCC = g++
# library paths
LIBS = -L/usr/share/boost_1_58_0/lib/ -lboost_serialization
# compile flags
LDFLAGS = -g
.SUFFIXES: .cpp
default: $(OUT)
.cpp.o:
$(CCC) $(INCLUDES) $(CCFLAGS) $< -o $#
$(OUT): $(OBJ)
ar rcs $(OUT) $(OBJ)
#depend: dep
#dep:
# makedepend -- $(CFLAGS) -- $(INCLUDES) $(SRC)
clean:
rm -f $(OBJ) $(OUT) Makefile.bak
-include $(DEPS:%.o=%.d)
Make passes environment variables to the makefile processor, so you can create make variables based on them.
INC_PATHS := ../include/ .
LIBS += boost_serialization
ifeq ($(OS),"Windows_NT")
INC_PATHS += ../include/ C:/boost_1_59_0/libs
LIBS += boost_serialization
else
INC_PATHS += /usr/local/include /usr/share/boost_1_58_0/lib/
endif
And then
INCLUDES = $(prepend -I,$(INC_PATHS))
or something like that. I'm not in front of make to ensure the syntax is exactly correct, but it should get you moving in the right direction.
(On Linux, trying to set up SDL) I'm having a time with makefiles, I'm finding them hard to learn. Here is the error I'm getting.
g++: error: game.exe: No such file or directory
make: *** [game.exe] Error 1
Here is my makefile. (Any suggestions on making it better would be great. I've just kind of slapped together whatever I could find to work.)
#Game Make file
TARGET = game.exe
OBJS = App.o\
App_OnInit.o\
App_OnEvent.o\
App_OnLoop.o\
App_OnRender.o \
App_OnCleanup.o\
SDL_CFLAGS := $(shell sdl-config --cflags)
SDL_LDFLAGS := $(shell sdl-config --libs)
CFLAGS = -Wall -o
LIBS =
LDFLAGS =
$(TARGET): $(OBJS)
g++ $(CFLAGS) $(SDL_CFLAGS) $# $(LDFLAGS) $(OBJS) $(SDL_LDFLAGS) $(LIBS)
%.o: src/%.cpp
g++ -c $(SDL_CFLAGS) $< $(SDL_LDFLAGS)
.PHONY: clean
clean:
rm -f $(TARGET) $(OBJS)
You could either exchange $(CFLAGS) and $(SDL_CFLAGS) in the rule to make $(TARGET) or better remove -o from CFLAGS and put it directly before $#:
...
CFLAGS = -Wall
...
$(TARGET): $(OBJS)
g++ $(CFLAGS) $(SDL_CFLAGS) -o $# $(LDFLAGS) $(OBJS) $(SDL_LDFLAGS) $(LIBS)
-o option should immediately precede the name of the executable file to be produced. In your original Makefile it is part of $(CFLAGS) and is followed by the C flags of the SDL library. Therefore the compiler tries to link in game.exe (the $#) instead of producing an executable file by that name.