Any way to use variables as rules and prerequisites in GNU Make? - c++

Question

I'm trying to set up my Makefile in such a way that I can define all of the inputs and outputs in some variables so I only have to write a single rule to compile the project. This allows me to minimize Makefile code and still have control over what is in my project. This is the relevant snippet of code:
ROOT_OBJS= \
$(B)/main.o \
$(B)/src1.o
ROOT_SRC= \
$(SRC)/main.cpp \
$(SRC)/src1.cpp
$(TARGET) : $(ROOT_OBJS)
$(LD) $(LD_FLAGS) $^ -o $#
$(ROOT_OBJS) : $(ROOT_SRC)
$(CXX) $(CFLAGS) $< -o $#
This mostly works except for the $< part in the second rule, it always uses main.cpp. Is there any fix to this or am I going about this the wrong way?
EDIT: for clarification, this is the output I expect:
g++ main.cpp -o main.o
g++ src1.cpp -o src1.o
This is the output I get:
g++ main.cpp -o main.o
g++ main.cpp -o src1.o
I am aware this is because $< takes the first dependency, I thought make would be smart enough to figure it out because the .o behavior is what I want.
$^ is not what I am looking for. I want gcc to make a separate object file for each cpp file.

Answer 1

$< always takes the first prerequisite. Since your rule expands to
$(B)/main.o $(B)/src1.o : $(SRC)/main.cpp $(SRC)/src1.cpp
$(CXX) $(CFLAGS) $< -o $#
$(SRC)/main.cpp is always that first prerequisite. There is no magical connection between $(B)/main.o and $(SRC)/main.cpp as far as make is concerned.
If you want your rules to make this connection, you have to code it into the rules. There are several ways to get this right. The most straight forward is to write separate rules for each target:
$(B)/main.o : $(SRC)/main.cpp
$(CXX) $(CFLAGS) $< -o $#
$(B)/src1.o : $(SRC)/src1.cpp
$(CXX) $(CFLAGS) $< -o $#
You can also use a pattern rule like this:
$(B)/%.o : $(SRC)/%.cpp
$(CXX) $(CFLAGS) $< -o $#
Here, $< does the right thing because $(SRC)/%.cpp is parameterized with the pattern, so it will expand to the correct source file.
The biggest gun you have is generating the individual rules:
STEMS := main src1
$(foreach stem,$(STEMS), \
$(eval $(B)/$(stem).o: $(SRC)/$(stem).cpp ; $(CXX) $(CFLAGS) $< -o $#))
Here I loop over all the words in $(STEMS) with the $(foreach) intrinsic function call and generate one rule per iteration with the $(eval) function call. This is GNU Make syntax, only, other make implementations are likely not to have these features. However, it is the most general and flexible way to tell make what to do. GNU Make's function call syntax is turing complete, so you can perform any calculations you need to come up with the correct rules. Readability will suffer, though, so use this with care.