Concurrent signal assignment with vector in VHDL - concurrency

Question

I'm trying to compile this code using GHDL and I get the error: '=>' is expected instead of 'not'. I want the code to not have any processes, neither implicit ones.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY decoder IS PORT
(c, b, a, g : IN std_logic;
y : OUT std_logic_vector(7 DOWNTO 0));
END decoder;
ARCHITECTURE beh_decoder OF decoder IS
BEGIN
y <= "10000000" WHEN (g NOT (a AND b AND c)) ELSE
"01000000" WHEN ((a AND g) NOT (b AND c)) ELSE
"00100000" WHEN ((b AND g) NOT (a AND c)) ELSE
"00010000" WHEN ((a AND b AND g) NOT c) ELSE
"00001000" WHEN ((c AND g) NOT (a AND b)) ELSE
"00000100" WHEN ((a AND c AND g) NOT b) ELSE
"00000010" WHEN ((b AND c AND g) NOT a) ELSE
"00000001" WHEN ((a AND g) NOT (b AND c)) ELSE
"00000000";
END ARCHITECTURE beh_decoder;

Answer 1

The when expressions are using the NOT gate as multi-input gate.
g NOT (a AND b AND c)
If we substitute Q = (a AND b AND c) you have
g NOT Q
Which is not meaningful? And likely what GHDL is complaining about.
Did you want
g OR NOT (a AND b AND c)
or
g AND NOT (a AND b AND c)
Based on your comment, the new code might look like this. You will need to confirm the logic but it should compile.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY decoder IS PORT
(c, b, a, g : IN std_logic;
y : OUT std_logic_vector(7 DOWNTO 0));
END decoder;
ARCHITECTURE beh_decoder OF decoder IS
BEGIN
y <= "10000000" WHEN (g AND NOT (a AND b AND c)) ELSE
"01000000" WHEN ((a AND g) AND NOT (b AND c)) ELSE
"00100000" WHEN ((b AND g) AND NOT (a AND c)) ELSE
"00010000" WHEN ((a AND b AND g) AND NOT c) ELSE
"00001000" WHEN ((c AND g) AND NOT (a AND b)) ELSE
"00000100" WHEN ((a AND c AND g) AND NOT b) ELSE
"00000010" WHEN ((b AND c AND g) AND NOT a) ELSE
"00000001" WHEN ((a AND g) AND NOT (b AND c)) ELSE
"00000000";
END ARCHITECTURE beh_decoder;