The file tree in my C++ project is like this:
project/
source/
main.cpp (with int main() function)
a.cpp
a.h
b.cpp
...
obj/
Makefile
But when I compile it, it throws an error: "In function _start': (.text+0x20): undefined reference to main'"
My makefile is:
EXECUTABLE = name_of_program
CXX = g++
CXXFLAGS = -Wall -Isource
LIBS =
SRC_DIR = source
OBJ_DIR = obj
SRC = $(wildcard $(SRC_DIR)/*.cpp)
OBJ = $(SRC:$(SRC_DIR)/%.cpp=$(OBJ_DIR)/%.o)
.PHONY: all clean
all: $(EXECUTABLE)
$(EXECUTABLE): $(OBJ)
$(CXX) -o $# $^ $(LIBS)
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(CXXFLAGS) -o $# $<
$(CXX) $(CXXFLAGS) -o $# -c $<
clean:
rm $(OBJ)
Which things should I correct in order to make it compile correctly? I know it's a compiler error but I'm sure it's about Makefile.
I don't have enough of your source to reproduce the problem, but by inspection, it looks like you have an extra line here:
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(CXXFLAGS) -o $# $<
$(CXX) $(CXXFLAGS) -o $# -c $<
Remove the first line so you don't try to link each object file independently.
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(CXXFLAGS) -o $# -c $<
Related
I have one Makefile to build an executable and a library. Executable consists of a lot of source files and library consists of one .cpp file. The difference between compilation of executable and library is -fPIC option.
There is a compilation rule:
%.o : %.cpp
$(CXX) -c $(CXXFLAGS) $< -o $#
all: $(TARGET) $(TARGET_LIB)
$(TARGET): $(OBJS)
$(CXX) $(LDFLAGS) -o $# $^
$(TARGET_LIB): $(LIBOBJS)
$(CXX) $(LDFLAGS) -fPIC -shared -o $# $^
I tried to add compilation rule for library and got this:
lib.o : lib.cpp
$(CXX) -fPIC -c $(CXXFLAGS) $< -o $#
%.o : %.cpp
$(CXX) -c $(CXXFLAGS) $< -o $#
all: $(TARGET) $(TARGET_LIB)
$(TARGET): $(OBJS)
$(CXX) $(LDFLAGS) -o $# $^
$(TARGET_LIB): $(LIBOBJS)
$(CXX) $(LDFLAGS) -fPIC -shared -o $# $^
Unfortunately, only lib is compiled in this case. Second rule is omitted.
How can I use a rule for one file and different rule for group of other files?
If you just run make without a target, the first target gets built. So just put all back at the top and it should work fine.
I recently got feedback that my Makefile doesn't call the required flags. This is a snippet of my Makefile.
CXX = g++
CXXFLAGS = -Wall
all: testFacility testCode testRunway testSiteNumber airport distance
testFacility: testFacility.cpp Facility.o gcdistance.o
$(CXX) -o $# $^
Does the flag "-Wall" get called when I type Make?
No, it needs to be referenced directly:
$(CXX) $(CXXFLAGS) -o $# $^
You probably want to define something to compile all those .cpp files too:
%.o: %.cpp
$(CXX) $(CXXFLAGS) -c -o $# $<
testFacility: testFacility.o Facility.o gcdistance.o
$(CXX) $(CXXFLAGS) -o $# $^
I know it has already been discussed a lot, but I'm getting a bit crazy and cannot figured it out by myself.
I'm trying to learn how to create makefiles, and I'm having problems in defining a makefile for files in different folders.
This is what I would like to obtain, after compiling:
/makefile
/test.exe
/src/factorials.cpp
/src/main.cpp
/src/hello.cpp
/obj/factorials.o
/obj/main.o
/obj/hello.o
/include/functions.h
What is wrong with this makefile?
C++ = g++
FILENAME = test
SOURCES_PATH = src/
SRC = $(SOURCES_PATH)factorial.cpp $(SOURCES_PATH)main.cpp $(SOURCES_PATH)hello.cpp
OBJ = factorial.o main.o hello.o
all: test.exe
test.exe: $(OBJ)
$(C++) $(OBJ) -o $(FILENAME) -Iinclude
%.o:
$(C++) -c $(SOURCES_PATH)$*.cpp -Iinclude
clean:
rm -f test.exe
Everything goes correctly, but it gives me error trying to compile src/all.cpp. Besides, I don't know how to say to g++ to put .o files into obj/ folder.
Thanks a lot!
You should fix your .o rule as follows
obj/%.o: $(SOURCES_PATH)/%.cpp
$(CC) $(CXXFLAGS) $< -o $#
Alternatively $(vpath) can be used to resolve where make looks up the source (prerequisite) files for a target:
vpath += $(SOURCES_PATH)
obj/%.o: %.cpp
$(CC) $(CXXFLAGS) $< -o $#
So it seems I was able to obtain the result by using the following makefile
C++ = g++
FILENAME = test
OBJS = obj/factorial.o obj/hello.o obj/main.o
INC = -Iinclude/
vpath+= src
$(FILENAME): $(OBJS)
$(C++) $(OBJS) -o $# $(INC)
obj/%.o: %.cpp
$(C++) -o $# -c $< $(INC)
all: $(FILENAME)
clean:
rm -rf objs/*.o *~ $(FILENAME).exe
Thanks! :)
I have this working Makefile and I would like to improve it:
CXX = g++
RM = rm -f
CXXFLAGS = -O2 -s -Wall -std=c++11
LDFLAGS = -Wl,-z,relro
SRCS = target1.cpp target2.cpp target3.cpp utils.cpp
OBJS = $(subst .cpp,.o,$(SRCS))
.PHONY: all target1 target2 target3 clean
all: target1 target2 target3
target1: target1.o utils.o
$(CXX) $(CXXFLAGS) $(LDFLAGS) $^ -o $# $(LDLIBS)
target2: target2.o utils.o
$(CXX) $(CXXFLAGS) $(LDFLAGS) $^ -o $# $(LDLIBS)
target3: target3.o utils.o
$(CXX) $(CXXFLAGS) $(LDFLAGS) $^ -o $# $(LDLIBS)
clean:
$(RM) $(OBJS)
My questions are:
Every target needs utils.o. Is it possible to avoid writing 3 times the same lines for target1/target2/target3?
I would like to separate sources, objects and binaries (Makefile in ./, binaries in ./, sources in src/, objects in obj/). What is the best solution in order to avoid writing target1: obj/target1.o obj/utils.o and so on?
Thanks!
1) Yes, you can use a pattern rule:
target%: target%.o utils.o
$(CXX) $(CXXFLAGS) $(LDFLAGS) $^ -o $# $(LDLIBS)
2) It really isn't that bad:
target%: obj/target%.o obj/utils.o
$(CXX) $(CXXFLAGS) $(LDFLAGS) $^ -o $# $(LDLIBS)
You can avoid those two obj/ prefixes, but it really isn't worth the trouble.
I am learning to create a makefile. My folder structure looks like this..
Project
bin //this is where the executable "e" is kept
e
obj //this is where the obj files generated are kept
Node.o
Node1.o
src //this is where .cpp files resides
Folder
Node.cpp
Folder2
Node1.cpp
include //this is where .hhp files resides
Folder
Node.hpp
Folder2
Node1.hpp
makefile
I am using Ubuntu 12.04 and trying to compile it using g++. The makefile resides in the project folder along with folders: src, include, obj and bin
My makefile looks like this
CC = g++
DEBUG = -g
CFLAGS = -Wall -c $(DEBUG)
LFLAGS = -Wall $(DEBUG)
TARGET = bin/
OBJ = obj/
INCLUDE = include/
SRC = src/
SOURCES=$(wildcard $(SRC)**/*.cpp $(SRC)*.cpp)
HEADERS=$(wildcard include/**/*.hpp include/*.hpp)
OBJECTS=$(patsubst %.cpp,$(OBJ)%.o,$(notdir $(SOURCES)))
All : $(TARGET)e
$(TARGET)e : make_dir $(OBJECTS)
$(CC) $(LFLAGS) $(OBJECTS) -o $#
$(OBJ)Node.o : $(SRC)Folder/Node.cpp $(HEADERS)
$(CC) $(CFLAGS) -I$(INCLUDE) $< -o $#
$(OBJ)Node1.o : $(SRC)Folder2/Node1.cpp $(HEADERS)
$(CC) $(CFLAGS) -I$(INCLUDE) $< -o $#
make_dir:
mkdir -p obj bin
clean :
-rm -rf bin
-rm -rf obj
-rm -f e *.o *~
This piece of code runs just fine but what I would like to do is to replace the below code snippets
$(OBJ)Node.o : $(SRC)Folder/Node.cpp $(HEADERS)
$(CC) $(CFLAGS) -I$(INCLUDE) $< -o $#
$(OBJ)Node1.o : $(SRC)Folder2/Node1.cpp $(HEADERS)
$(CC) $(CFLAGS) -I$(INCLUDE) $< -o $#
with some thing more like
%.o : %.cpp $(HEADERS)
$(CC) $(CFLAGS) -I$(INCLUDE) $< -o $#
Something that generalizes the whole feeding and mapping. In other words, automate the makefile in a way I shouldn't worry or edit until the hierarchy is disturbed.
$(OBJ)/%.o : $(SRC)Folder/%.cpp $(HEADERS)
$(CC) $(CFLAGS) -I$(INCLUDE) $< -o $#