Makefile: automatically compile source for every included header - c++

Question

Can I configure my makefile in a way that it automatically compiles and links foo/bar.cpp if a target includes #include "foo/bar.hpp"?
Details: I have a makefile for a project structured like this:
src/
|-- program1/
| |-- main.cpp
| |-- makefile
|-- modules/
| |-- module1/
| | |-- foo.cpp
| | |-- foo.hpp
| |-- module1/
| | |-- bar.cpp
| | |-- bar.hpp
Currently my makefile for program1 contains a list of all the *.cpp files of all the modules it uses, which is kind of hard and error-prone to maintain and to keep in sync with my includes.
However, in my code, following the #include commands would provide an exact dependency-tree. For every *.hpp there is a corresponding *.cpp that I need to compile and link.
Can this process of compilation be automated via the makefile? May auto-dependencies help me out?
The makefile in question:
# compiler settings
CXX = g++
CXXFLAGS = -std=c++14
# object file generation path
tmpDir = .objs
# modules path
modPath = ../modules
# Names of modules and files to be compiled
names := \
main.o \
module1/foo.o \
module2/bar.o
# prepend tmpDir
names := $(addprefix $(tmpDir)/, $(names))
# Linking
main: $(names)
$(CXX) $(CXXFLAGS) -o main $^
# Rule for main file
$(tmpDir)/main.o: main.cpp
#mkdir -p $(tmpDir)
$(CXX) $(CXXFLAGS) -c main.cpp -o $# -I "$(modPath)"
# rules for module files
$(tmpDir)/%.o: $(modPath)/%.cpp
mkdir -p $(dir $#)
$(CXX) $(CXXFLAGS) -c $< -o $#
clean:
rm -rf *.o main $(tmpDir)
I'd like to avoid to manually set names.

Answer 1

A common way to automate generating the file names is using a $(wildcard ...) or some $(shell ...) command to scan the directories.
Based on the Makefile you linked I think you can track the dependencies using GCC with the -MMD -MP flags something like this:
# compiler settings
CXX = g++
# use flags to generate dependency files
CXXFLAGS = -std=c++14 -MMD -MP
# object file generation path
tmpDir = .objs
# modules path
modPath = ../modules
# Names of modules and files to be compiled
names := main.o
names += $(patsubst $(modPath)/%.cpp,%.o,$(shell find $(modPath) -iname "*.cpp"))
# prepend tmpDir
names := $(addprefix $(tmpDir)/, $(names))
# there should be a dep file for every object file
deps := $(patsubst %.o,%.d,$(names))
all: main
# Linking
main: $(names)
$(CXX) $(CXXFLAGS) -o main $^
# Rule for main file
$(tmpDir)/main.o: main.cpp
#mkdir -p $(tmpDir)
$(CXX) $(CXXFLAGS) -c main.cpp -o $# -I "$(modPath)"
# rules for module files
$(tmpDir)/%.o: $(modPath)/%.cpp
mkdir -p $(dir $#)
$(CXX) $(CXXFLAGS) -c $< -o $#
# include the dependencies if they exist
-include $(deps)
clean:
rm -rf *.o main $(tmpDir) $(deps)
Every compile command that uses the -MMD -MP flags will generate a dependency file corresponding to the output file (except with a .d extension).

Answer 2

regarding: *Currently my makefile for program1 contains a list of all the *.cpp files of all the modules it uses, which is kind of hard and error-prone to maintain and to keep in sync with my includes.
However, in my code, following the #include commands would provide an exact dependency-tree. For every *.hpp there is a corresponding *.cpp that I need to compile and link.
Can this process of compilation be automated via the makefile? May auto-dependencies help me out?*
In the makefile, you could use the output of a call to the find command to obtain a list of all the (for instance) *.cpp files in the directories below the modules directory rather than hard-coding the list.

Answer 3

I refined Galik's answer a bit. Now it behaves much like what I was searching for.
Instead of defining names manually, I invoke a search for files. The results then filters to match only *.cpp files that have a *.hpp file with the same name. This ignores all files containing the tests:
# find *.hpp files
names := $(shell find $(modPath) -iname "*.hpp")
# replace extension .hpp -> .cpp
names := $(patsubst %,%.cpp,$(basename $(names)))
# filter nonexistent *.cpp files
names := $(wildcard $(names))