Now I'm learning c++. While trying to execute makefile, I'm getting error like this
Makefile:45: invalid syntax in conditional. Stop.
My system configurations are :
OS:- Ubuntu
OpenWRT SDK
I'm trying to build the SDK in ubuntu OS system.
Here I'm adding the makefile code, which I have tried.
include $(TOPDIR)/rules.mk
PKG_NAME:=helloworld
PKG_VERSION:=0.0.1
PKG_RELEASE:=1
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)
include $(INCLUDE_DIR)/package.mk
define Package/helloworld
SECTION:=base
CATEGORY:=Utilities
DEFAULT:=n
TITLE:=This is my first project
URL:=http://unwireddevices.com
# Other packages your program needs (our doesn't need anything, so let's comment it out)
# DEPENDS:=+libstdcpp
endef
define Package/helloworld/description
This! Is! My! First! Project!
endef
define Build/Prepare
mkdir -p $(PKG_BUILD_DIR)
$(CP) ./src/* $(PKG_BUILD_DIR)/
endef
define Build/Configure
$(call Build/Configure/Default,--with-linux-headers=$(LINUX_DIR))
endef
define Package/helloworld/install
$(INSTALL_DIR) $(1)/usr/bin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/helloworld $(1)/usr/bin/
endef
$(eval $(call BuildPackage, helloworld))
In your Makefile, first line seems to be over-indented.
Follow make file guidelines and use tabs and spaces properly.
Related
I have a makefile to generate some headers and cpp files from a yaml file.
../api/%.h ../api/%.cpp : ../idl/%.yml
$(info Generating api files from $<)
$(IDL_TO_CPP_EXE) --input $< --output $(basename $#)
IDL_HEADERS=$(IDL_INPUTS:../idl/%.yml=../api/%.h)
IDL_CPPS=$(IDL_INPUTS:../idl/%.yml=../api/%.cpp)
all: $(IDL_HEADERS) $(IDL_CPPS)
$(info The dependencies are $(IDL_HEADERS) $(IDL_CPPS))
IDL_INPUTS +=../idl/common_api/CommonTypes.yml
When I run it, it outputs the following, but without generating the .h and .cpp file. I've checked they aren't there, so it's not a timestamp issue.
The dependencies are ../api/common_api/CommonTypes.h ../api/common_api/CommonTypes.cpp
make: Nothing to be done for 'all'.
If I manually expand the variables to the following, then it suddenly starts to work! The console output from the logging is exactly the same, and I've been careful to avoid things like hidden characters.
all: ../api/common_api/CommonTypes.h ../api/common_api/CommonTypes.cpp
$(info The dependencies are $(IDL_HEADERS) $(IDL_CPPS))
Why is this makefile working with explicit dependencies, but not with variables?
UPDATE:
all: $(IDL_HEADERS) $(IDL_CPPS)
$(info The dependencies are $^)
$(info The dependencies should be $(IDL_HEADERS) $(IDL_CPPS))
outputs:
The dependencies are
The dependencies should be ../api/common_api/CommonTypes.h ../api/common_api/CommonTypes.cpp
make: Nothing to be done for 'all'.
This turned out to be an ordering problem. When the all rule is parsed, I hadn't set the IDL_INPUTS variable.
IDL_INPUTS gets set later, and the the all rule was run after that, showing the new updated values.
I am trying to compile bt from NPB. I am getting the attached errorCompilation Error . I have also attached the make file I am using.
What am I doing wrong in this case?
MakeFile:
SHELL=/bin/sh
BENCHMARK=bt
BENCHMARKU=BT
include ../config/make.def
OBJS = bt.o \
${COMMON}/c_print_results.o ${COMMON}/c_timers.o ${COMMON}/c_wtime.o
include ../sys/make.common
# npbparams.h is included by header.h
# The following rule should do the trick but many make programs (not gmake)
# will do the wrong thing and rebuild the world every time (because the
# mod time on header.h is not changed. One solution would be to
# touch header.h but this might cause confusion if someone has
# accidentally deleted it. Instead, make the dependency on npbparams.h
# explicit in all the lines below (even though dependence is indirect).
# header.h: npbparams.h
${PROGRAM}: config ${OBJS}
${CLINK} ${CLINKFLAGS} -o ${PROGRAM} ${OBJS} ${C_LIB}
.c.o:
${CCOMPILE} $<
bt.o: bt.c header.h npbparams.h
clean:
- rm -f *.o *~ mputil*
- rm -f npbparams.h core
Seems missing ../sys/setparams
Which should be an executable file, and takes bt A as input arguments.
It might be a depended tool should be built at first. I've tried a search on github, and could find some projects containing, ../sys/setparams.c, maybe, these are what you need.
Hope it helps you.
I have created the following little makefile snippet. Note: I have made this a minimal example of my problem so it is a pointless makefile.
TARGET = none
OBJ_BASE_DIR = obj
# Linux x86 c++ compiler
.PHONY: build_cpp_x86Linux
build_cpp_x86Linux: TARGET = x86Linux
build_cpp_x86Linux: build
OBJ_DIR = $(addsuffix /$(TARGET),$(OBJ_BASE_DIR))
$(info TARGET IS: $(TARGET))
$(info OBJ_DIR IS: $(OBJ_DIR))
build: $(OBJ_DIR)/test.o
#echo building, OBJ_DIR: $(OBJ_DIR)
# pattern rule
$(OBJ_DIR)/%.o:
#echo "compiling $#"
Here is the output of calling make:
TARGET IS: none
OBJ_DIR IS: obj/none
compiling obj/none/test.o
building, OBJ_DIR: obj/x86Linux
From the output you can see that it is trying to compile obj/none/test.o, but what I want it to do is try to compile obj/x86Linux/test.o. I am not quite sure what is going on here. I think I understand that the makefile expands the variables on the first pass (which would result in TARGET=none), but I thought that it would re-expand the variables again once I have called the target build_cpp_x86Linux which sets the value of TARGET to x86Linux...
What I am doing wrong here and how should this be done?
You could also use:
TARGET?=none
And then override on the command line TARGET=x86Linux
You can also use ifdef or other scanning if operations to set different variables based on these arguments or environment variables.
I'm building a C++ project using GNU Make (version 3.80). The makefile is auto-generated from the tool I'm using (IBM Rational Rhapsody). An example of this makefile is at the end of this post.
This makefile has a mechanism that allows me to specify a directory for object files (the OBJ_DIR variable). If this is set, the variable CREATE_OBJ_DIR is set up with the command if not exist $(OBJ_DIR) mkdir $(OBJ_DIR). This is then called for each object file in the project.
Running this makefile without setting an object file directory works as expected; the code is compiled without issues. But running it with OBJ_DIR set to 'build' causes the following error:
C:\Users\XXX\AppData\Local\Temp\make52963.sh: C:\Users\XXX\AppData\Local\Temp\make52963.sh: line 2: syntax error: unexpected end of file
C:\Tools\XXX\x86-win32\bin\make.exe: *** [build/Example.o] Error 2
I'm certain the issue is within the rule for '/build/Example.o', when $(CREATE_OBJ_DIR) is called. If I manually edit the rule and replace $(CREATE_OBJ_DIR) with mkdir $(OBJ_DIR), the command is executed correctly. If I then replace it with if not exist build mkdir build directly, to eliminate any issues due to variable expansion, the same error appears.
Other things I have tried:
Run a cmd shell with the same environment variables set as when the makefile is called, and attempted to run the if not exist build mkdir build command. No issues with this.
Ensure that no trailing characters are present in the command run within the makefile. None appear to be present.
My only conclusion at this point is that something about if statements causes the makefile to fail, but I'm not sure what. Is there anything else I should try to track down the source of this problem? Am I missing something obvious.
Let me know if more details are required.
Note: I've edited this makefile pretty heavily, so it's just to give an idea of what I'm using, and probably won't execute. Some of the environment variables below are set up in a batch file prior to calling make, but I'm confident they're not part of the issue I'm seeing, as the makefile works correctly except in the situation described above.
CPU = XXX
TOOL = gnu
INCLUDE_QUALIFIER=-I
LIB_CMD=$(AR)
LINK_CMD=$(LD)
CPP_EXT=.cpp
H_EXT=.h
OBJ_EXT=.o
EXE_EXT=.out
LIB_EXT=.a
TARGET_NAME=Example
all : $(TARGET_NAME)$(EXE_EXT) Example.mak
TARGET_MAIN=Example
LIBS=
INCLUDE_PATH=
ADDITIONAL_OBJS=
OBJS= \
build/Example.o \
OBJ_DIR=build
ifeq ($(OBJ_DIR),)
CREATE_OBJ_DIR=
else
CREATE_OBJ_DIR= if not exist $(OBJ_DIR) mkdir $(OBJ_DIR)
endif
build/Example.o : src/Example.cpp
#echo Compiling src/Example.cpp
$(CREATE_OBJ_DIR)
#$(CXX) $(C++FLAGS) -o build/Example.o src/Example.cpp
You are thinking to complex. A far simpler solution here is to use:
mkdir -p $(OBJ_DIR)
This will also make it work if OBJ_DIR=my/little/obj/dir/deep/down/the/rabit/hole.
Look at the following Makefile:
OBJ_DIR=foo
CREATE_OBJ_DIR= if not exist $(OBJ_DIR) mkdir $(OBJ_DIR)
$(info CREATE_OBJ_DIR=$(CREATE_OBJ_DIR))
all:
$(CREATE_OBJ_DIR)
and it's output:
% make
CREATE_OBJ_DIR=if not exist foo mkdir foo
if not exist foo mkdir foo
/bin/sh: 1: Syntax error: end of file unexpected (expecting "then")
Makefile:8: recipe for target 'all' failed
make: *** [all] Error 2
Your "if" statement is simply not valid shell syntax. On the other hand if OBJ_DIR is empty then CREATE_OBJ_DIR is empty and that is valid.
I use GNU make for building reports (LaTeX for source, python for figures, etc.). For targets, I use extensively pattern matching, for example:
all : sample1_test1.png sample2_test1.png sample2_test.png
sample%_test1.png : sample%.dat
python gen_figure.py $< $# --test 1
sample%_test2.png : sample%.dat
python gen_figure.py $< $# --test 2
Now, to simplify the rules I would like to use multiple pattern groups (like regex groups) and use the matches separately in the build rule, for example:
all : sample1_test1.png sample2_test1.png sample2_test.png
sample(?P<Sample>[0-9]+)_test(?P<Test>[0-9]+).png : sample$(<Sample>).dat
python gen_figure.py $< $# --test $(<Test>)
(the syntax is arbitrary, but the point is that I can define two different match groups called Sample and Test and use them as parameters to my script).
How would I achieve this in make or another build system (waf, scons etc.)?
To do it in GNU make, you can use one of two different "metaprogramming" models supported by GNU make:
Auto-generated include files. In your main makefile, add -include generated.mk then write a makefile rule with the target generated.mk (probably listing Makefile as a prerequisite), where the recipe generates the appropriate targets based on the list of targets. You have the full power of the shell to construct your target lists however you want. Every time you modify the makefile, the included file will be rebuilt then GNU make will automatically re-exec itself so you don't have to do anything extra.
Use GNU make's $(eval ...) function, probably combined with $(call ...) and $(foreach ...), to automatically evaluate rules. To do this you define a "template" for the rule using define ... enddef, with variables installed where you want to provide arguments, then use $(call ...) to instantiate them, use $(eval ...) on the result of the call, and do it in a loop for each target. Something like: $(foreach T,$(TARGETS),$(eval $(call DEFINERULE,$(T))))
Here's an example of method 1. Suppose you have this predefined content in your makefile:
TESTS := sample1_test1.png sample2_test1.png sample2_test.png
Then you can use this makefile to get something like the above:
all: $(TESTS)
-include generated.mk
generated.mk : Makefile
#rm -f '$#'
#for t in $(TESTS); do \
eval `echo "$$t" | sed 's/^sample\([0-9]*\)_test\([0-9]*\).*/sample=\1 test=\2/'`; \
echo "$$t : sample$$sample.dat ; python gen_figure.py \$$< \$$# --test $$test" >> '$#'; \
done
Note I just wrote this off the top of my head but I think it will work.