Makefile Creation Difficulty - c++

I had to merge two codes (TestOne.cpp + TestTwo.cpp), one of them already has its makefile (TestOne.cpp), but the other has only .h included, each of these .h has no cpp, all the code is on the .h (TestTwo.cpp)
for the makefile it's like this , and it work:
CC = g++
CFLAGS = -std=c++11
test: main.o hung.o
$(CC) -o test main.o hung.o
hung.o: Hungarian.cpp Hungarian.h
$(CC) -c Hungarian.cpp -o hung.o
main.o: testMain.cpp Hungarian.h
$(CC) $(CFLAGS) -c testMain.cpp -o main.o
clean:
-rm main.o hung.o
and the other one (TestTwo.cpp) it's also work by compiling like that :
g++ TestTwo.cpp -o test `pkg-config opencv --libs`
I have to create a new makefile using the first and introducing the seconde commande g++ ... how should i do ?

Related

C++ makefile not linking

EXENAME = prog1
OBJS = link.o main.o
CXX = clang++
CXXFLAGS = -Wall -Wextra
LD = clang++
all : $(EXENAME)
$(EXENAME) : $(OBJS)
$(LD) $(OBJS) -o $(EXENAME)
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) main.cpp
link.o : link.h link.cpp
$(CXX) $(CXXFLAGS) link.cpp
clean :
-rm -f *.o $(EXENAME)
This is the make file I got but all the function in link can't be called in main. I tried many different ways doesn't work. This works
prog1: main.cpp link.h link.cpp
clang++ -Wall -Wextra -o prog1 main.cpp link.cpp
But I suppose is not the right way to do this?
It would help if you provided at least some of the errors you got (probably the first few).
Your compiler invocation for building object files is wrong. Without any other flags specified, the compiler will try to take all the input files and create an executable out of them. So this rule:
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) main.cpp
expands to this compilation line:
clang++ -Wall -Wextra main.cpp
The compiler will attempt to compile and link the main.cpp file (only, because that's all that's listed here) into an executable named a.out (by default).
You need to add the -c option to your compile lines if you want to build an object file rather than link a program:
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) -c main.cpp
Ditto for building link.o.
Even better would be to simply use make's built-in rules for compiling object files rather than writing your own; in that case your entire makefile could just be:
EXENAME = prog1
OBJS = link.o main.o
CXX = clang++
CXXFLAGS = -Wall -Wextra
all : $(EXENAME)
$(EXENAME) : $(OBJS)
$(CXX) $(CXXFLAGS) $(OBJS) -o $(EXENAME)
main.o : link.h
link.o : link.h
clean :
-rm -f *.o $(EXENAME)

C++ makefile while seperate the declaration and implementation

I wrote a small simple SQL interpreter in C++, in my main.cpp
the code is something like
#include "lexer.h"
#include "parser.h"
#include "interpreter.h"
using namespace std;
int main(int argc, char* argv[]) {
//my code
}
In lexer.h,parser.h, interpretor.h, each contain the declaration and implementation of a class with the same name of the header file.My question is how should I write my makefile so that I can separate the declaration and implementation, for example, declaration in lexer.h, implementation in lexer.cpp ?
The simplest way to do it is like below
interpreter: main.cc lexer.cc parser.cc interpreter.cc
g++ -o interpreter main.cc lexer.cc parser.cc interpreter.cc -I
but sometimes is useful to use different targets. This is because if you modify a single file in your project, you don't have to recompile everything, only what you modified.So you can do like below
Using dependencies
all: interpreter
interpreter: main.o lexer.o parser.o interpreter.o
g++ main.o lexer.o parser.o interpreter.o -o interpreter
main.o: main.cc
g++ -c main.cc
lexer.o: lexer.cc
g++ -c lexer.cc
parser.o: parser.cc
g++ -c parser.cc
interpreter.o: interpreter.cc
g++ -c interpreter.cc
clean:
rm -rf *o hello
Using variables and comments
We can also use variables when writing Makefiles
# Implementing a new sql lexer the variable CC will be
# the compiler to use.
CC=g++
# these flags will be passed to the compiler.
CFLAGS=-c -Wall
all: interpreter
interpreter: main.o lexer.o parser.o interpreter.o
$(CC) main.o lexer.o parser.o interpreter.o -o interpreter
main.o: main.cc
$(CC) $(CFLAGS) main.cc
lexer.o: lexer.cc
$(CC) $(CFLAGS) lexer.cc
parser.o: parser.cc
$(CC) $(CFLAGS) parser.cc
interpreter.o: interpreter.cc
$(CC) $(CFLAGS) interpreter.cc
clean:
rm -rf *o hello

MakeFile : Header in different Directory - Error

I am trying to avoid relative paths in header declaration of C++ files. So, I had used the makefile by following an online example. But I am getting error. Please check the code and help me to resolve this
COMPILER = g++
IDIR = ./include
CXXFLAGS += -I$(IDIR)
CFLAGS += -I$(IDIR)
EXEC = hello
OBJECTS = main.o factorial.o hello.o
all: $(EXEC)
(---- I had also used CFLAGS instead of CXXFLAGS below but the same result###)
$(EXEC): $(OBJECTS)
$(COMPILER) $(CXXFLAGS) $(OBJECTS) -o $(EXEC)
main.o: main.cpp ./include/functions.h
$(COMPILER) $(CXXFLAGS) -c main.cpp
factorial.o: main.cpp ./include/functions.h
$(COMPILER) $(CXXFLAGS) -c factorial.cpp
hello.o: main.cpp ./include/functions.h
$(COMPILER) $(CXXFLAGS) -c hello.cpp
Error:
make: * No rule to make target 'include / functions.h "
required by "main.o" to create. Closing.
Directory Structure is
- main.cpp
- factorial.cpp
- hello.cpp
- MakeFile.mk
- +include (dir)
----->functions.h
main.cpp contains ----include "functions.h"---- in the header declaration
You are not using h files as a source files.
there should only be:
main.o: main.cpp
$(COMPILER) $(CXXFLAGS) -c main.cpp
edited:
I copy your folder content and write simple application where hello.cpp have a simple void function, factorial.cpp have simple int-returning function ane main.cpp have int main() and uses this functions, include.h hafe declarations of these two dummy functions.
Now. My makefile looks:
COMPILER = g++
IDIR = ./include
CXXFLAGS += -I$(IDIR)
EXEC = hello
OBJECTS = main.o factorial.o hello.o
all: $(EXEC)
$(EXEC): $(OBJECTS)
$(COMPILER) $(CXXFLAGS) $(OBJECTS) -o $(EXEC)
main.o: main.cpp factorial.o hello.o
$(COMPILER) -c $(CXXFLAGS) $^ -o $#
factorial.o: factorial.cpp
$(COMPILER) -c $(CXXFLAGS) $^ -o $#
hello.o: hello.cpp
$(COMPILER) -c $(CXXFLAGS) $^ -o $#
download for my sample
That should help You!
This is a pure make error message. The error is not related to the content of any .cpp or .h file. The error actually can come only from the content of the Makefile, and of the presence or absence of the files named in it.
As per this error message, make states that it cannot find the file include/functions.h. Double check it actually is here, with correct name and matching case.
For debugging purpose you can add the following lines to your Makefile:
./include/functions.h:
touch $#
It will instruct make to create an empty include/functions.h file if it's missing.

Having issues with a Makefile for a c++ project written in Xcode

I wrote this c++ project in Xcode, and now I have to create a Makefile so that it compiles properly. Here is the Makefile:
CC = g++
CFLAGS =
PROG = TrainStation
MAIN = main.cpp
OBJS = ArrivalEvent.o DepartureEvent.o Event.o EventCoordinator.o InSwitchEvent.o ListItem.o OrderedList.o OutSwitchEvent.o PriorityQueue.o Train.o
# compiling rules
# WARNING: *must* have a tab before each definition
$(PROG): $(OBJS) main.o # The error was leaving out main.o from this line
$(CC) $(CFLAGS) $(OBJS) main.o -o $(PROG)
ArrivalEvent.o: ArrivalEvent.cpp ArrivalEvent.h EventCoordinator.h InSwitchEvent.h Event.h EventCoordinator.h Train.h
$(CC) $(CFLAGS) -c ArrivalEvent.cpp -o ArrivalEvent.o
DepartureEvent.o: DepartureEvent.cpp DepartureEvent.h OutSwitchEvent.h Event.h EventCoordinator.h Train.h
$(CC) $(CFLAGS) -c DepartureEvent.cpp -o DepartureEvent.o
Event.o: Event.cpp Event.h EventCoordinator.h ListItem.h
$(CC) $(CFLAGS) -c Event.cpp -o Event.o
EventCoordinator.o: EventCoordinator.cpp EventCoordinator.h OrderedList.h Event.h Train.h PriorityQueue.h ArrivalEvent.h InSwitchEvent.h
$(CC) $(CFLAGS) -c EventCoordinator.cpp -o EventCoordinator.o
InSwitchEvent.o: InSwitchEvent.cpp InSwitchEvent.h DepartureEvent.h Event.h EventCoordinator.h Train.h
$(CC) $(CFLAGS) -c InSwitchEvent.cpp -o InSwitchEvent.o
ListItem.o: ListItem.cpp ListItem.h
$(CC) $(CFLAGS) -c ListItem.cpp -o ListItem.o
OrderedList.o: OrderedList.cpp OrderedList.h ListItem.h
$(CC) $(CFLAGS) -c OrderedList.cpp -o OrderedList.o
OutSwitchEvent.o: OutSwitchEvent.cpp OutSwitchEvent.h Train.h InSwitchEvent.h Event.h EventCoordinator.h
$(CC) $(CFLAGS) -c OutSwitchEvent.cpp -o OutSwitchEvent.o
PriorityQueue.o: PriorityQueue.cpp PriorityQueue.h OrderedList.h
$(CC) $(CFLAGS) -c PriorityQueue.cpp -o PriorityQueue.o
Train.o: Train.cpp Train.h ListItem.h
$(CC) $(CFLAGS) -c Train.cpp -o Train.o
main.o: $(MAIN) Train.h OrderedList.h PriorityQueue.h EventCoordinator.h
$(CC) $(CFLAGS) -c $(MAIN) -o main.o
clean:
rm -f $(PROG) $(OBJS)
I have written Makefiles before, but never one with so many files to coordinate, and it seems that it is skipping the rule for main.o [EDIT: I updated my Makefile but now receive this different error]
$ make
g++ -c ArrivalEvent.cpp -o ArrivalEvent.o
g++ -c DepartureEvent.cpp -o DepartureEvent.o
g++ -c Event.cpp -o Event.o
g++ -c EventCoordinator.cpp -o EventCoordinator.o
g++ -c InSwitchEvent.cpp -o InSwitchEvent.o
g++ -c ListItem.cpp -o ListItem.o
g++ -c OrderedList.cpp -o OrderedList.o
g++ -c OutSwitchEvent.cpp -o OutSwitchEvent.o
g++ -c PriorityQueue.cpp -o PriorityQueue.o
g++ -c Train.cpp -o Train.o
g++ main.o ArrivalEvent.o DepartureEvent.o Event.o EventCoordinator.o InSwitchEvent.o ListItem.o OrderedList.o OutSwitchEvent.o PriorityQueue.o Train.o -o TrainStation
i686-apple-darwin11-llvm-g++-4.2: main.o: No such file or directory
make: *** [TrainStation] Error 1
I know this is an error with g++, and that it probably has to do with me leaving out a file somewhere or not linking it, but I can't seem to figure out what is going wrong. Perhaps someone with fresh eyes may be able to spot the problem?
EDIT: PROBLEM SOLVED
My problem was that $(OBJS) doesn't contain main.o, so the rule for $(PROG) doesn't depend on main.o at all. Once I added main.o to the rule for $(PROG), then the rule for main.o is executed correctly.
After MAIN = main.cpp you do never use this variable to compile and link the main.cpp file.
Change this:
$(CC) $(CFLAGS) $(OBJS) -o $(PROG)
to this:
$(CC) $(CFLAGS) $(OBJS) main.o -o $(PROG)

Problem with makefile making .gch files instead of.o files

So, I'm making a program to test the efficiency of certain data structures. I have all the .h files and I made a very terrible makefile that probably is wrong, although it seems to work up to a point. Instead of making .o files it makes .gch files, so when it tries to acces all the .o files they are not found. This is my makefile
prog1: main.o dsexceptions.o BinarySearchTree.o SplayTree.o RedBlackTree.o AvlTree.o
g++ -Wall -g -o prog1 main.o dsexceptions.h.gch BinarySearchTree.h.gch SplayTree.h.gch RedBlackTree.h.gch AvlTree.h.gch
main.o: main.cpp AvlTree.h RedBlackTree.h SplayTree.h BinarySearchTree.h dsexceptions.h
g++ -Wall -g -c main.cpp
#shape.o: shape.cpp shape.h grid.h
# g++ -Wall -g -c shape.cpp
dsexceptions.o: dsexceptions.h
g++ -Wall -g -c dsexceptions.h
BinarySearchTree.o: BinarySearchTree.h dsexceptions.h
g++ -Wall -g -c BinarySearchTree.h
SplayTree.o: SplayTree.h dsexceptions.h
g++ -Wall -g -c SplayTree.h
RedBlackTree.o: RedBlackTree.h dsexceptions.h
g++ -Wall -g -c RedBlackTree.h
AvlTree.o: AvlTree.h dsexceptions.h
g++ -Wall -g -c AvlTree.h
clean:
rm -f main main.exe main.o dsexceptions.o BinarySearchTree.o SplayTree.o RedBlackTree.o AvlTree.o *.gch
You don't want to feed your .h files to the compiler. Only compile the .cpp file, which should include your .h files. (The .gch files are precompiled headers.) You don't need .o files for your headers, just #include them in your .cpp file.
prog1: main.o
g++ -Wall -g -o prog1 main.o
main.o: main.cpp AvlTree.h RedBlackTree.h SplayTree.h BinarySearchTree.h dsexceptions.h
g++ -Wall -g -c main.cpp
clean:
rm -f prog1 main.o
You already have the solution from bstpierre, but just for fun here's my version of your makefile:
CC = g++ -Wall -g -o $#
MODULE = AvlTree BinarySearchTree RedBlackTree SplayTree
OBJECTS = $(addsuffix .o,$(MODULES))
prog1: main.o dsexceptions.o $(OBJECTS)
$(CC) $^
main.o: $(addsuffix .h,$(MODULES))
$(OBJECTS) main.o : %.cpp %.h dsexceptions.h
$(CC) -c $&lt
clean:
rm -f main main.exe *.o *.gch
And just for good measure, here is my SConstruct, because SCons's so much better :)
Program('main.cpp') # Yeah, it's that simple :)
You can look at SCons here.