I want a makefile to compile a library (DRNG) with another makefile located in a subdirectory.
Here is what I have done :
.PHONY: out.exe clean drng
DRNG_DIR=./libdrng-1.0/
clean:
make clean -C $(DRNG_DIR)
#rm -f out.exe *.o
drng:
cd $(DRNG_DIR) && ./configure
make -C $(DRNG_DIR)
CC=g++
CFLAGS=-Wall -Werror -std=c++11
LDFLAGS=-L$(DRNG_DIR) -ldrng
objects=...
%.o: %.cpp
$(CC) -c $(CFLAGS) $*.cpp -o $*.o
out.exe: drng main.o $(objects)
$(CC) $(CFLAGS) $^ -o $# $(LDFLAGS)
I get an error : g++: drng: no such file or directory
Make is trying to compile 'drng'. I thought putting it in PHONY was supposed to prevent that.
Related
I have a makefile which compiles a program with many dependencies like this:
CXX=g++
IDIR=lib
CFLAGS=-Wall -O2 -std=c++11 -I$(IDIR)
UDIR=utils
CFILES=Utils.cpp Structs.cpp Registry.cpp Dealer.cpp
CFILES:=$(patsubst %.cpp,$(UDIR)/%.cpp,$(CFILES))
DEPS=$(wildcard $(IDIR)/*.hh)
ODIR=obj
OBJ:=$(patsubst $(UDIR)/%.cpp,$(ODIR)/%.o,$(CFILES))
CDIR=strategies
EXTRA_CFILES=$(wildcard $(CDIR)/Strategy*.cpp)
CFILES += $(EXTRA_CFILES)
EXTRA_OBJ:=$(patsubst $(CDIR)/%.cpp,$(ODIR)/%.o,$(EXTRA_CFILES))
OBJ += $(EXTRA_OBJ)
all: create_header environment.exe
create_header:
chmod +x create_headers.sh
bash create_headers.sh
$(ODIR)/%.o: $(UDIR)/%.cpp $(DEPS)
$(CXX) -c -o $# $< $(CFLAGS)
$(ODIR)/%.o: $(CDIR)/%.cpp $(DEPS)
$(CXX) -c -o $# $< $(CFLAGS)
environment.o: environment.cpp $(OBJ)
$(CXX) -c -o $# $< $(CFLAGS)
environment.exe: environment.o $(OBJ)
$(CXX) $(CFLAGS) $^ -o $#
m='Auto'
git_upload:
git add -A
git commit -m "$(m)"
git push
.PHONY: clean
clean:
rm -rf $(ODIR)/*.o *.exe
However, when I type make, it is always compiling everything. I only want it to compile the dependencies when a change has been made, either to header or implementation files. The problem is, it is always compiling everything even though I haven't changed anything.
I am trying to build a Makefile that will build a shared library with g++ and I find that it is not evaluating the OBJECTS variable. This is on Ubuntu 18.04 and all the files are in the same current directory. Secondly it is completely skipping the source file compilation and proceeding directly to evaluate the linking instruction. As a clarification I am using GNU Make 4.1
Here is what I get when I type make all
g++ -shared -pthread -o tree.so
g++: fatal error: no input files
compilation terminated.
Makefile:12: recipe for target 'tree.so' failed
make: *** [tree.so] Error 1
Here is my Makefile code
CC=g++
CFLAGS = -I/usr/local/include -Wall -std=c++17 -O3 -march=native -Ofast -ftree-vectorize
LIBS=-shared -pthread
SOURCES=$(wildcard *.cpp)
OBJECTS=$(wildcard *.o)
TARGET=tree.so
all:$(TARGET)
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(OBJECTS) $(TARGET)
$(OBJECTS):$(SOURCES)
$(CC) -c -g $(CFLAGS) $(SOURCES)
clean:
rm -f $(OBJECTS) $(TARGET)
If you only have the *.cpp files in your directories, then there is not any *.o yet, so your $(wildcard *.o) will expand to nothing.
What you want is to get the *.cpp files and compute the corresponding *.o files:
OBJECTS=$(patsubst %.cpp,%.o,$(SOURCES))
or equivalently:
OBJECTS=$(SOURCES:.cpp=.o)
Now, your compiler command is not the best one, because if you touch any source file all will be compiled. You can use instead:
$(OBJECTS): %.o: %.cpp
$(CC) -c -g $(CFLAGS) $< -o $#
So that only the touched files are actually rebuilt.
Also you have the linking command wrong. It should be:
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(TARGET) $(OBJECTS)
because the argument to the -o option is the output file, that is the target.
I am trying to compile my C++ code using the GNU compiler under Linux using the following Makefile
CXX=gcc #icpc
RM=rm -f
CPPFLAGS=-g -O3 -fopenmp
CFLAGS= -Wall -c
OPENMP = -fopenmp
BIN = theVeecode_$(CXX)
LIBS= -L /path-to-boost/boost_1_53_0/stage/lib/ -lboost_regex
CPPSRCS=mathtools.cpp time_.cpp read_input.cpp vee_ao_calc.cpp vee_mo_calc.cpp write_int2e.cpp memory_check.cpp
OBJS=$(subst .cpp,.o,$(CPPSRCS))
OBJS+=$(COBJS)
all: $(BIN)
$(BIN): $(OBJS)
$(CXX) main.cpp $(OPENMP) -o $(BIN) $(OBJS) $(LIBS)
clean:
$(RM) $(OBJS) $(BIN)
dist-clean: clean
$(RM) $(BIN)
When I run the make command, I get the following error messages:
gcc -g -O3 -fopenmp -c -o read_input.o read_input.cpp
read_input.cpp:9:27: error: boost/regex.hpp: No such file or directory
read_input.cpp: In function 'void input::read_n_occ()':
read_input.cpp:95: error: 'boost' has not been declared
read_input.cpp:95: error: 'regex_search' was not declared in this scope
make: *** [read_input.o] Error 1
The read_input.cpp file starts with
#... // other includes
#include <boost/regex.hpp>
using namespace std;
namespace xxx
{
//some code here
}
The library path "/path-to-boost/boost_1_53_0/stage/lib/" contains the files
libboost_regex.a, libboost_regex.so and libboost_regex.so.1.53.0.
I don't understand why the compiler doesn't find the library files. Does anyone have any ideas why it's not working and how to fix it?
Thanks in advance.
As it turned out, the problem was in the Makefile. More specifically, the path to the boost library was not included during the compilation of the .cpp files using boost. Fixed it by adding the library explicitly in the compilation step:
%.o: %.cpp $(DEPS)
$(CXX) -c -o $# $< $(CPPFLAGS) $(LIBS)
Finally, the Makefile is as follows:
CXX=gcc #icpc
RM=rm -f
CPPFLAGS=-g -O3 -fopenmp
OPENMP = -fopenmp
BIN = theVeecode_$(CXX)
LIBS= -I /path-to-boost/boost_1_53_0/
LIBS+= -L /path-to-boost/boost_1_53_0/stage/lib/ -lboost_regex
CPPSRCS=mathtools.cpp time_.cpp read_input.cpp vee_ao_calc.cpp vee_mo_calc.cpp write_int2e.cpp memory_check.cpp
OBJS=$(subst .cpp,.o,$(CPPSRCS))
DEPS=Vector3.h mathtools.h memory_check.h read_input.h time_.h vee_ao_calc.h vee_mo_calc.h write_int2e.h
%.o: %.cpp $(DEPS)
$(CXX) -c -o $# $< $(CPPFLAGS) $(LIBS)
$(BIN): $(OBJS)
$(CXX) main.cpp $(OPENMP) -o $(BIN) $(OBJS) $(LIBS)
clean:
$(RM) $(OBJS) $(BIN)
dist-clean: clean
$(RM) $(BIN)
To get the word out there;
For my case, I was missing the libboost-dev package.
On debian, you can install it with sudo apt install libboost-dev
I have seen questions like these on SO but everyone has different answers and directory structures that aren't working for me.
My makefile:
CC = g++
DEBUG = -g -std=c++11
TARGET = main
OBJECT_FILES = BingResultSet.o main.o
INC_PATH = -I HTTPClientLib/include
LIB_PATH = -L HTTPClientLib/lib/
start: clean BingResultSet.o main.o
$(CC) $(DEBUG) $(INC_PATH) $(LIB_PATH) $(OBJECT_FILES) -o $(TARGET)
rm -f *.o
BingResultSet.o: BingResultSet.cpp BingResultSet.h
$(CC) $(DEBUG) $(INC_PATH) $(LIB_PATH) -c BingResultSet.cpp
main.o: main.cpp
$(CC) $(DEBUG) $(INC_PATH) $(LIB_PATH) -c main.cpp
clean:
rm -f $(OBJECT_FILES) $(TARGET)
My file structure:
/Desktop/DataMiner/.cpp, .h, and makefile
/Desktop/DataMiner/HTTPClientLib/include/HTTPClient.h
/Desktop/DataMiner/HTTPClientLib/lib/HTTPClient.a
What's the correct way to link my static lib in my makefile?
Here's my $0.02:
there was no static library involved. Assuming you meant the .o files
you mix dependencies and build rules, instead, avoid repeating build rules:
$(TARGET): $(OBJECT_FILES)
$(CXX) $(DEBUG) $(INC_PATH) $^ -o $# $(LIB_PATH)
%.o: %.cpp
$(CXX) $(DEBUG) $(INC_PATH) -c $< -o $#
You used CC for a C++ compiler. That's strange. Use CXX
You used LDFLAGS when you were just compiling
You hardcoded the source and destination paths. Instead use the automatic variables ($^, $< for source; $# for destination)
You tried to hardcode header dependencies. That's error-prone and messes up source specification (you don't want $^ to list .h files in your command line...). Instead, use gcc -MM¹ to generate the dependencies for you!
Next, do a conditional include of those dependencies:
.depends:
$(CXX) -MM $(CXXFLAGS) -c *.cpp > $#
-include .depends
It's usually handy to keep the .o files so you can speed up builds. Of course, this was not a good plan until you generated the header dependencies automatically. If you insist, you can comment the .PRECIOUS target. Intermediate targets are automatically deleted by GNU Make
Here's the integrated offering I ended up with:
CXX = g++
TARGET = main
OBJECT_FILES = BingResultSet.o main.o
INC_PATH = -I HTTPClientLib/include
LIB_PATH = -L HTTPClientLib/lib/
CPPFLAGS = -g -std=c++11
CPPFLAGS+= $(INC_PATH)
# standard derived flags:
CXXFLAGS+=$(CPPFLAGS)
LDFLAGS+=$(LIB_PATH)
start: .depends $(TARGET)
$(TARGET): $(OBJECT_FILES)
$(CXX) $(CXXFLAGS) $^ -o $# $(LDFLAGS)
%.o: %.cpp
$(CXX) $(CXXFLAGS) -c $< -o $#
clean:
rm -f .depends $(OBJECT_FILES) $(TARGET)
# to keep the .o files:
.PRECIOUS: $(OBJECT_FILES)
.depends:
$(CXX) -MM $(CXXFLAGS) -c *.cpp > $#
-include .depends
On a very simple sample set of files you get:
$ make clean
rm -f .depends BingResultSet.o main.o main
$ make
g++ -MM -g -std=c++11 -I HTTPClientLib/include -c *.cpp > .depends
g++ -I HTTPClientLib/include -c BingResultSet.cpp -o BingResultSet.o
g++ -I HTTPClientLib/include -c main.cpp -o main.o
g++ -I HTTPClientLib/include BingResultSet.o main.o -o main -L HTTPClientLib/lib/
$ cat .depends
BingResultSet.o: BingResultSet.cpp BingResultSet.h
main.o: main.cpp BingResultSet.h
test.o: test.cpp
¹ (or similar, see man-page)
I've tried numerous attempts to move my .o files to my obj folder, but no matter what I do, it simply just doesn't work.
Judging from the makefile provided, what is the best method to move .o files to a specified folder?
BIN = bin/
OBJ = obj/
TARGET = opengl_03
DEPS = main.o displayinit.o initializer.o algorithms.o matrix3f.o window.o vertex3.o
CC = g++
CFLAGS = -g
LIBS = -lglut -lGLEW -lGL
INCLUDEPATH = -L/usr/include/ -L/usr/lib/ -L/usr/lib/x86_64-linux-gnu/
$(TARGET) : $(DEPS)
$(CC) $(CFLAGS) -o $(BIN)$(TARGET) $(DEPS) $(LIBS) $(INCLUDEPATH)
displayinit.o : displayinit.cpp displayinit.h
$(CC) $(LIBS) $(INCLUDEPATH) -c displayinit.cpp && mv displayinit.o $(OBJ)displayinit.o
initializer.o : initializer.cpp initializer.h
$(CC) $(LIBS) $(INCLUDEPATH) -c initializer.cpp $(OBJ)
algorithms.o : algorithms.cpp algorithms.h
$(CC) -c algorithms.cpp $(OBJ)
matrix3f.o : matrix3f.cpp matrix3f.h
$(CC) $(LIBS) $(INCLUDEPATH) -c matrix3f.cpp $(OBJ)
vertex3.o : vertex3.cpp vertex3.h
$(CC) $(LIBS) $(INCLUDEPATH) -c vertex3.cpp $(OBJ)
window.o : window.cpp window.h
$(CC) $(LIBS) $(INCLUDEPATH) -c window.cpp $(OBJ)
main.o : main.cpp
$(CC) $(LIBS) $(INCLUDEPATH) -c main.cpp $(OBJ)
To specify where the object is created use -o
window.o : window.cpp window.h
$(CC) $(LIBS) $(INCLUDEPATH) -c window.cpp -o $(OBJ)/$#
Here is what you could do:
specify the directory where you want the object files to go
OBJDIR = objdir
Create a list of object files that need to be compiled, from the list of all .cpp files by replacing .cpp with .o and add the prefix $(OBJDIR)/ to it:
OBJ = $(addprefix $(OBJDIR)/, $(patsubst %.cpp, %.o, $(wildcard *.cpp)))
So your $(OBJ) will look like: objdir/window.o objdir/main.o and so on
Add a target to create the directory if it does not exist:
$(OBJDIR):
mkdir $(OBJDIR)
Make the directory target before you make your main target:
all: $(OBJDIR) myapp
Rule to compile all the .o object files in $(OBJDIR) from .cpp files in the current directory:
$(OBJDIR)/%.o: %.cpp
$(GCC) $(CPPFLAGS) -c $< -o $#
This will result in something like:
g++ -c main.cpp -o objdir/main.o
Your main target is unchanged:
$(TARGET): $(OBJ)
$(GCC) $(LDFLAGS) -o $# $^
This will look like:
g++ -o myapp objdir/window.o objdir/main.o
For completeness add clean target to cleanup objects:
clean:
#rm -f $(TARGET) $(wildcard *.o)
#rm -rf $(OBJDIR)
And define .PHONY targets, e.g. these will be made even if directories or files with the same name exist:
.PHONY: all clean
So it should look like:
OBJDIR = objdir
OBJ = $(addprefix $(OBJDIR)/, $(patsubst %.cpp, %.o, $(wildcard *.cpp)))
TARGET = my app
.PHONY: all clean
all: $(OBJDIR) $(TARGET)
$(OBJDIR):
mkdir $(OBJDIR)
$(OBJDIR)/%.o: %.cpp
$(GCC) $(CPPFLAGS) -c $< -o $#
$(TARGET): $(OBJ)
$(GCC) $(LDFLAGS) -o $# $^
clean:
#rm -f $(TARGET) $(wildcard *.o)
#rm -rf $(OBJDIR)
And if you have files such as main.cpp and a.cpp this is what make would do:
> ls
Makefile a.cpp main.cpp
> make
mkdir objdir
g++ -I. -c a.cpp -o objdir/a.o
g++ -I. -c main.cpp -o objdir/main.o
g++ -o myapp objdir/a.o objdir/main.o
> ls
Makefile a.cpp main.cpp objdir myapp
> make clean
> ls
Makefile a.cpp main.cpp
And if you want to read more details about any of the above have a look at GNU make doc page
In response to the comment, some more tips:
1) Remove some redundancy
This part is very repetitive:
displayinit.o : displayinit.cpp displayinit.h
$(CC) $(LIBS) $(INCLUDEPATH) -c displayinit.cpp && mv displayinit.o $(OBJ)displayinit.o
initializer.o : initializer.cpp initializer.h
$(CC) $(LIBS) $(INCLUDEPATH) -c initializer.cpp $(OBJ)
algorithms.o : algorithms.cpp algorithms.h
$(CC) -c algorithms.cpp $(OBJ)
# ...
You can replace it by two parts:
1) a more general rule, something like:
%.o: %.cpp
$(CC) -c $(LIBS) $(INCLUDEPATH) $< -o $#
$< and $# are automatic variables, $# expands to the name of currently built target and $< is the first dependency ($^ would be "all the dependencies", there are more such vars - see the Make manual).
2) any additional deps (i.e. headers):
displayinit.o: displayinit.h
matrix3f.o: matrix3f.h
main.o: main.h window.h displayinit.h
#etc
Note: For each .o file, its dependencies should contain:
the .cpp from which it is built (the dependency is from the general rule),
all .h files which are included from that .cpp files (which you need to add later).
Note that you omitted the latter part in your original makefile. This would cause you some problems one day.
2) Generate the deps automatically
Basically every time you add an #include in any of your files, you'd need to modify your makefile to reflect the new dependency between .cpp/.o and .h files. This is very troublesome, but fortunately there are automated solutions for that. There are two approaches for C/C++ here:
Use your compiler to generate the dependencies for you (gcc/g++ -MM for instance).
Use an additional tool such as makedepend.
Either way, you need to include that set of dependencies dynamically in the makefile. This needs some trickery, but once you have it, you never have to worry about dependencies. Have a google for "C++ makefile dependencies", there should be plenty of resources.
Here's a to-the-point doc about Make.
Following worked for me :
g++ test.cpp -c -o obj/test.o
So in your case, for example, you would make the following modification :
displayinit.o : displayinit.cpp displayinit.h
$(CC) $(LIBS) $(INCLUDEPATH) -c displayinit.cpp -o displayinit.o $(OBJ)displayinit.o
Also, for the final compilation, you need to pick up the .o files from the obj folder, so modify DEPS to have bin/<xyz>.o. Alternatively, you could cd obj before the final build :
$(TARGET) : $(DEPS)
cd $(OBJ)
$(CC) $(CFLAGS) -o ../$(BIN)$(TARGET) $(DEPS) $(LIBS) $(INCLUDEPATH)
In the first target, add the command to move the files to the desired dir.
$(TARGET) : $(DEPS)
$(CC) $(CFLAGS) -o $(BIN)$(TARGET) $(DEPS) $(LIBS) $(INCLUDEPATH)
mv *.o obj/