I'm trying to figure out how to use makefile and subdirectories. But unluck till now. I want to put all the .o files in an "build" subdirecotry, all the .cpp should be in an "src" and the executable file in an "bin" file.
And this makefile was my attempt:
PROG = prog1
BINPATH = bin/
CC = g++
CPPFLAGS = -Wall -pedantic -ansi -Iinclude
OBJS = main.o calc.o show.o
BUILDPATH = build/
SRCPATH = src/$(PROG):$(BUILDPATH)$(OBJS)
$(CC) -o $(BINPATH)$(PROG) $(BUILDPATH)$(OBJS)
$(BUILDPATH)main.o:
$(CC) $(CPPFLAGS) -c $(SRCPATH)main.cpp
$(BUILDPATH)cacula.o:calc.h
$(CC) $(CPPFLAGS) -c $(SRCPATH)calc.cpp
$(BUILDPATH)show.o:show.h
$(CC) $(CPPFLAGS) -c $(SRCPATH)show.cpp
clean:
rm -f core $(BINPATH)$(PROG) $(BUILDPATH)$(OBJS)
The most immedite problem is that you are manipulating the variables wrong.
OBJS = main.o calc.o show.o
BUILDPATH = build/
So far, so good, but $(BUILDPATH)$(OBJS) will expand to build/main.o calc.o show.o, which is not what you want. Try this:
OBJS := main.o calc.o show.o
BUILDPATH := build/
OBJS := $(addprefix $(BUILDPATH), $(OBJS))
Then you can use OBJS like this:
$(PROG): $(OBJS)
$(CC) -o $(BINPATH)$(PROG) $(OBJS)
There are several other ways to improve this makefile, but this should be enough to get it working.
Related
When I run make, I get the following error:
make: *** No rule to make target Menu.h', needed by Menu.o'. Stop.
Here is my Makefile:
PROG = sim
CURR_PATH = ~/Projects/restaurant/cpp/
CC = g++
CPPFLAGS = -g -v -Wall $(LOCAL_INCLUDES) -I$(BOOST_ROOT)
ODIR = ./bin
SDIR = ./src
LOCAL_INCLUDES = $(patsubst %,-I$(CURR_PATH)src/%,$(PKG_DIRS))
PKG_DIRS = $(shell ls $(SDIR))
FIND_SRC_FILES = $(notdir $(wildcard $(SDIR)/$(pkg)/*.cpp))
SRC_FILES = $(foreach pkg,$(PKG_DIRS),$(FIND_SRC_FILES))
OBJ_FILES = $(patsubst %.cpp,%.o,$(SRC_FILES))
MAIN_OBJ = main.o
.PHONY : prog
prog : $(PROG)
all : ; $(info $$CPPFLAGS is [${CPPFLAGS}])#echo Hello world
$(PROG) : $(OBJ_FILES)
$(CC) $(CPPFLAGS) -o $(PROG) $(MAIN_OBJ)
%.o : %.cpp
$(CC) $(CPPFLAGS) -c $< -o $#
$(OBJ_FILES) : %.o : %.h
$(CC) $(CPPFLAGS) -c $(patsubst %.h,%.cpp,$<) -o $#
BTW, in case you're wondering what LOCAL_INCLUDES looks like, the output for the 'all' recipe is the following:
$CPPFLAGS is [-g -v -Wall -I~/Projects/restaurant/cpp/src/concurrent -I~/Projects/restaurant/cpp/src/containers -I~/Projects/restaurant/cpp/src/data -I~/Projects/restaurant/cpp/src/loader -I~/Projects/restaurant/cpp/src/main -I~/Projects/restaurant/cpp/src/people -I~/Projects/restaurant/cpp/src/sim -I/usr/local/boost_1_72_0]
Hello world
Sorry for the single line output, I am unaware of how to format in a more readable fashion. But as you can see, the directory data, which contains Menu.h, is being properly included. But for some reason, make is unable to find it. What could possibly be going wrong here?
Let me know if you need more information.
Cheers
The compiler knows how to find that header file. Make does not know how to find it, and Make is the one producing that error message.
I suggest you make this modification:
INCLUDE_DIRS = $(addprefix $(CURR_PATH)src/,$(PKG_DIRS))
LOCAL_INCLUDES = $(addprefix -I,$(INCLUDE_DIRS))
vpath %.h $(INCLUDE_DIRS)
(P.S. Your use of CURR_PATH and . is confusing, and data/ is a terrible place to put header files.)
EDIT:
All right, let's take this in stages. Step 1, try this makefile:
OBJ_FILES = Menu.o
INCLUDE_DIRS = ~/Projects/restaurant/cpp/src/data
vpath %.h $(INCLUDE_DIRS)
Menu.o:
$(OBJ_FILES) : %.o : %.cpp %.h
#echo building $# from $^
and tell us what happens. (If it doesn't work, tell us what happens.)
As aforementioned, make's vpath did not like the absolute path that it was being given. See below for my modified Makefile:
PROG = sim
CURR_PATH = ~/Projects/restaurant/cpp/
CC = g++
CPPFLAGS = -g -v -Wall $(LOCAL_INCLUDES) -I$(BOOST_ROOT)
ODIR = bin
# vpath only needs SDIR and PKG_DIRS!
SDIR = src
PKG_DIRS = $(shell ls $(SDIR))
INCLUDE_DIRS = $(addprefix $(CURR_PATH)src/,$(PKG_DIRS))
LOCAL_INCLUDES = $(addprefix -I,$(INCLUDE_DIRS))
FIND_SRC_FILES = $(notdir $(wildcard $(SDIR)/$(pkg)/*.cpp))
SRC_FILES = $(foreach pkg,$(PKG_DIRS),$(FIND_SRC_FILES))
OBJ_FILES = $(patsubst %.cpp,%.o,$(SRC_FILES))
MAIN_OBJ = main.o
vpath %.h $(addprefix $(SDIR)/,$(PKG_DIRS))
.PHONY : all
prog : $(PROG)
all : ; $(info $$CPPFLAGS is [${CPPFLAGS}])#echo Hello world
$(PROG) : $(OBJ_FILES)
$(CC) $(CPPFLAGS) -o $(PROG) $(MAIN_OBJ)
%.o : %.cpp
$(CC) $(CPPFLAGS) -c $< -o $#
$(OBJ_FILES) : %.o : %.h
$(CC) $(CPPFLAGS) -c $(patsubst %.h,%.cpp,$<) -o $#
I hope this helps other people that come across similar issues.
I have a C++ project with the following structure:
/Project
Makefile
/src (.cpp source files)
...
/include (.h header files)
...
/libs
...
/build (.o object files)
...
/tests (target .cpp files I want to compile)
test1.cpp
test2.cpp
test3.cpp
...
/bin (output directory for compiled files)
...
For the tests inside my test file, I would like to be able to
Compile them individually, e.g. "make test1", "make test2"
Compile them all at once
But I would like to be able to do this without needing to define new variables (e.g. TARGET1, TARGET2,...) for each new test file, nor add a bunch of new lines to my makefile for each new test file.
For example, right now I have something like:
CXX = g++
SRC_DIR = ./src
BUILD_DIR = ./build
LIB = -I libs
INC = -I include
SRCS = $(shell find $(SRC_DIR) -type f -name *.cpp)
OBJS = $(patsubst $(SRC_DIR)/%, $(BUILD_DIR)/%, $(SRCS:.cpp=.o))
TARGET1 ?= test1.cpp
TARGET2 ?= test2.cpp
TARGET3 ?= test3.cpp
all: $(OBJS)
$(CXX) ./tests/$(TARGET1).cpp $(LIB) $(INC) $^ -o ./bin/$(TARGET1)
$(CXX) ./tests/$(TARGET2).cpp $(LIB) $(INC) $^ -o ./bin/$(TARGET2)
$(CXX) ./tests/$(TARGET3).cpp $(LIB) $(INC) $^ -o ./bin/$(TARGET3)
$(TARGET1): $(OBJS)
$(CXX) ./tests/$(TARGET1).cpp $(LIB) $(INC) $^ -o ./bin/$(TARGET1)
$(TARGET2): $(OBJS)
$(CXX) ./tests/$(TARGET2).cpp $(LIB) $(INC) $^ -o ./bin/$(TARGET2)
$(TARGET3): $(OBJS)
$(CXX) ./tests/$(TARGET3).cpp $(LIB) $(INC) $^ -o ./bin/$(TARGET3)
$(BUILD_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(INC) -c -o $# $<
which does the job, but isn't very scalable. How could I do this scalably?
Make has some more tricks that you can use (not tested):
CXX = g++
SRC_DIR = src
BUILD_DIR = build
TEST_DIR = tests
BIN_DIR = bin
LIB = -I libs
INC = -I include
SRCS = $(wildcard $(SRC_DIR)/*.cpp)
OBJS = $(patsubst $(SRC_DIR)/%.cpp,$(BUILD_DIR)/%.o,$(SRCS))
TESTS = $(wildcard $(TEST_DIR)/*.cpp)
TARGETS = $(patsubst $(TEST_DIR)/%.cpp,$(BIN_DIR)/%,$(TESTS))
all: $(TARGETS)
$(TARGETS): $(BIN_DIR)/%: $(OBJS)
$(CXX) $(TEST_DIR)/$*.cpp $(LIB) $(INC) $^ -o $#
$(BUILD_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(INC) -c -o $# $<
The main trick here is the static pattern rule for $(TARGETS): in the recipe $* expands as the stem of the pattern. The other tricks are a simpler use of patsubst and the use of wildcard instead of the less efficient shell find. Note that this last one works only if your source files are flat in src, not if they are organized in a hierarchy of sub-directories.
But this does not answer your most tricky request: a way to invoke make testX instead of make bin/testX. So, here is the most tricky part:
SHORTERTARGETS = $(patsubst $(TEST_DIR)/%.cpp,%,$(TESTS))
.PHONY: $(SHORTERTARGETS)
# $(1): short target
define TARGETS_rule
$(1): $(BIN_DIR)/$(1)
endef
$(foreach t,$(SHORTERTARGETS),$(eval $(call TARGETS_rule,$(t))))
You can even use this foreach-eval-call to factorize other parts of your Makefile:
CXX = g++
SRC_DIR = src
BUILD_DIR = build
TEST_DIR = tests
BIN_DIR = bin
LIB = -I libs
INC = -I include
SRCS = $(wildcard $(SRC_DIR)/*.cpp)
OBJS = $(patsubst $(SRC_DIR)/%.cpp,$(BUILD_DIR)/%.o,$(SRCS))
TESTS = $(wildcard $(TEST_DIR)/*.cpp)
TARGETS = $(patsubst $(TEST_DIR)/%.cpp,$(BIN_DIR)/%,$(TESTS))
SHORTERTARGETS = $(patsubst $(TEST_DIR)/%.cpp,%,$(TESTS))
.PHONY: all $(SHORTERTARGETS)
all: $(TARGETS)
$(BUILD_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(INC) -c -o $# $<
# $(1): short target
define TARGETS_rule
$(1): $(BIN_DIR)/$(1)
$(BIN_DIR)/$(1): $(OBJS)
$(CXX) $(TEST_DIR)/$(1).cpp $(LIB) $(INC) $$^ -o $$#
endef
$(foreach t,$(SHORTERTARGETS),$(eval $(call TARGETS_rule,$(t))))
The most difficult to understand in this last version is the need of $$in the recipe (double expansion). But here the GNU make manual is your friend.
I have seen some examples of using makefile with multiple source directories but still could not implement it to my makefile.
Currently I have all source files at /src/ folder and I would like to be able compile subfolders in /src/ such as /src/modules.
I am using:
NAME = 'AI'
SRC = src
TGT = obj
PRG = application
INCLUDES = -Iinclude ...
LIBRARIES = -L ...
CXXFLAGS = -O2 -std=c++0x $(INCLUDES) $(LIBRARIES)
SOURCES = $(wildcard $(SRC)/*.cpp)
ENDFLAGS = -ljvm -lcurl
NOWARNINGS = -Wno-unused-variable -Wno-unused-result
OBJS = $(addprefix $(TGT)/, $(notdir $(SOURCES:.cpp=.o)))
$(TGT)/%.o: $(SRC)/%.cpp
$(CXX) $(CXXFLAGS) -c $< -o $# $(NOWARNINGS)
$(PRG)/$(NAME): $(OBJS)
$(CXX) $(LIBRARIES) $(OBJS) -o $# $(ENDFLAGS) $(NOWARNINGS)
I am trying to build excutables for multiple files which are built in the same way. When i run make all the excutables should be generated. I am getting error at prerequisites part of the macro.
CXX = g++
CXX_FLAGS = -g -Wall
LD_FLAGS =
INC_DIR = -I/my/path/include
SRC_DIR = .
LIB_DIR = -L$/my/path/lib
OBJ_DIR = obj
EXE_DIR = exe
SRCS := $(foreach s_dir, $(SRC_DIR), $(wildcard $(s_dir)/*.cpp))
OBJS := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRCS))
EXES := $(patsubst $(SRC_DIR)/%.cpp, $(EXE_DIR)/%.out, $(SRCS))
all: create_directories create_objects create_exes
create_directories:
#echo "Creating $(OBJ_DIR) and $(EXE_DIR)..."
#mkdir -p obj
#mkdir -p exe
create_objects:
$(foreach b_dir, $(OBJ_DIR), $(eval $(call build-objects, $(b_dir))))
create_exes:
$(foreach ot, $(EXE_DIR), $(eval $(call build-exes, $(ot))))
define build-objects
$1/%.o: %.cpp
$(CXX) $(CXX_FLAGS) $(INC_DIR) -MMD -MP -c $$< -o $$#
endef
define build-exes
$1/%.out:obj/%.o
$(CXX) $(LD_FLAGS) -o $# $(OBJS) $(LIB_DIR) -lmylib
endef
Is this a right way to do generate multiple exes or any other simple way?
If I'm reading this makefile right, then it's much too complicated.
First let's have a rule to build object files:
$(OBJ_DIR)/%.o: %.cpp
$(CXX) $(CXX_FLAGS) $(INC_DIR) -MMD -MP -c $< -o $#
Now if we're not sure about the existence of obj/, we could add a rule to create it, but for the moment let's just put in a failsafe (we'll come back to this later):
$(OBJ_DIR)/%.o: %.cpp
#mkdir -p $(OBJ_DIR)
$(CXX) $(CXX_FLAGS) $(INC_DIR) -MMD -MP -c $< -o $#
And a similar rule to build the executables:
$(EXE_DIR)/%.out: $(OBJ_DIR)/%.o
#mkdir -p $(EXE_DIR)
$(CXX) $(LD_FLAGS) -o $# $^ $(LIB_DIR) -lmylib
And finally (at the top) some variables, the lists of files, and the all rule:
CXX = g++
CXX_FLAGS = -g -Wall
LD_FLAGS =
INC_DIR = -I/my/path/include
SRC_DIR = .
LIB_DIR = -L$/my/path/lib
OBJ_DIR = obj
EXE_DIR = exe
SRCS := $(wildcard $(SRC_DIR)/*.cpp)
EXES := $(patsubst $(SRC_DIR)/%.cpp, $(EXE_DIR)/%.out, $(SRCS))
# Let the object files take care of themselves
all: $(EXES)
That's all you need. Once this is working perfectly, we can discuss refinements like rules for building directories.
Simply put: It's not finding the include paths:
CC = g++
OBJS = *.o #*/*.o
DEBUG = -g
PNAME = game
INCLUDES = -Iheaders
CFLAGS = -Wall $(DEBUG)
LFLAGS = -Wall -lsfml-graphics -lsfml-window -lsfml-system $(DEBUG)
all: build
build: $(OBJS)
$(CC) $(LFLAGS) $(OBJS) -o $(PNAME)
clean:
\rm *.o *~ $(PNAME)
.cpp:
$(CC) $(CFLAGS) $(INCLUDES) -c $(.SOURCE)
Your makefile looks pretty broken to me. Firstly, you probably want:
OBJS = $(patsubst %.cpp,%.o,$(wildcard *.cpp))
Secondly, your final rule needs to be something more like:
%.o: %.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c $^ -o $#