Substitution reference with .cpp and .c files [closed] - c++

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I know there a lot of questions about mixing .cpp and .c files into one makefile, but I haven't seen the issue of mixed substitution reference addressed. I am having issues with it.
My makefile is structure is based on this answer:
LIB=mylib.so
CPPSRCS += hello.cpp
CSRCS += goodbye.c
OBJS = $(CSRCS:.c=.o) $(CPPSRCS:.cpp=.o)
# Separate rules for .cpp and .c files, link together to form library.
# All pretty standard stuff and I am sure it will work if we goodbye.o and
# hello.o are present.
This doesn't work, and I get the old no rule to make target error. What am I doing wrong? How can I do substitution reference on two types of files into one variable?

Answer 1

In order to have a makefile work for both C and C++, you need separate rules for each language - although some rules are the same.
Another issue would be the linker. A C only project will use one linker and not the other.
I'm dumping my makefile here (it's from this project).
As you can see from this example, there are two different build rules, one for objects created with C file and another for objects created with C++. When the first one fails, the second one is attempted, so sharing a list of objects is made possible.
Also, you might notice that the C++ rule has this line $(eval CCL = $(CPP)) which sets the linker variable (CCL) to the C++ linker in projects where C++ is used. This way, when the build rule is called, it uses the correct linker.
Another thing to look at is the way this code deals with lists and extension substitution. Notice the use of the foreach, addsuffix and basename functions... this is distinctly more complex then the $(CSRCS:.c=.o) you suggested.
I would recommend you add a rule that displays the make variables, so you can debug any that have gone astray (see the demo), it a great way to learn as well as resolve issues.
A few words of warning about the makefile I'm pasting here...
It works for both C and C++ (mixed) projects and it's almost "plug and play", but you must to change the folder names and target files to fit your folder structure.
Also, notice that it will delete the whole of your project if you define the temporary folder as the project folder (it's defined as tmp for a reason, as it makes cleanup real easy).
In the future I might update it so any src subfolders are automatically added, but at the moment I need that extra control to exclude some folders.
This makefile is mostly a work of laziness... I hate updating makefiles all the time, so I have a low-cost makefile that mostly calculates everything on it's own... unless I change the project's folder structure or need different libraries.
NAME=demo
OUT_ROOT=./tmp
TMP_ROOT=./tmp
SRC_ROOT=.
SRC_EXTRA_FOLDERS=src src/http
LIBS=-pthread -lssl -lcrypto
INCLUDE=/usr/local/include
CC=#gcc
CPP=#g++
DB=#lldb
OPTIMIZATION=O3
#auto computed values
BIN = $(OUT_ROOT)/$(NAME)
SRCDIR = $(SRC_ROOT) $(foreach dir, $(SRC_EXTRA_FOLDERS), $(addsuffix /,$(basename $(SRC_ROOT)))$(dir))
SRC = $(foreach dir, $(SRCDIR), $(wildcard $(addsuffix /, $(basename $(dir)))*.c*))
BUILDTREE =$(foreach dir, $(SRCDIR), $(addsuffix /, $(basename $(TMP_ROOT)))$(basename $(dir)))
OBJS = $(foreach source, $(SRC), $(addprefix $(TMP_ROOT)/, $(addsuffix .o, $(basename $(source)))))
CCL = $(CC)
# the C flags
CFLAGS=-Wall -g -$(OPTIMIZATION) -std=c11 $(foreach dir,$(INCLUDE),$(addprefix -I, $(dir))) $(foreach dir,$(SRCDIR),$(addprefix -I, $(dir)))
CPPFLAGS= -Wall -$(OPTIMIZATION) -std=c++11 $(foreach dir,$(INCLUDE),$(addprefix -I, $(dir))) $(foreach dir,$(SRCDIR),$(addprefix -I, $(dir)))
$(NAME): build
build: $(OBJS)
$(CCL) -o $(BIN) $^ -$(OPTIMIZATION) $(LIBS)
$(TMP_ROOT)/%.o: %.c
$(CC) -o $# -c $^ $(CFLAGS)
$(TMP_ROOT)/%.o: %.cpp
$(CPP) -o $# -c $^ $(CPPFLAGS)
$(eval CCL = $(CPP))
clean:
-#rm $(BIN)
-#rm -R $(TMP_ROOT)
-#mkdir -p $(BUILDTREE)
execute:
#$(BIN)
run: | clean build execute
db: | clean build
$(DB) $(BIN)
vars:
#echo "BIN: $(BIN)"
#echo ""
#echo "SRCDIR: $(SRCDIR)"
#echo ""
#echo "SRC: $(SRC)"
#echo ""
#echo "BUILDTREE: $(BUILDTREE)"
#echo ""
#echo "OBJS: $(OBJS)"
#echo ""
#echo "CFLAGS: $(CFLAGS)"
#echo ""
#echo "CPPFLAGS: $(CPPFLAGS)"
As par Toby Speight's suggestion, I added the pipe sign (|) to mark the prerequisites as ordered, for all the concurrency people out there.