Makefile: automatic generation of dependencies for binaries - c++

Question

I would like to "completely" automate the process of dependency generation in a project's Makefile. So far, I have followed this tutorial on automatic dependencies, which works very nicely. There is only one catch: this only works for head-file dependencies, so it will automatically detect if say bin_1.o depends on header_1.h as well as header_2.h. However, I can directly translate header-file dependencies to object-file dependencies. Say, one of the automatically generated dependency files says
bin_1.o: bin_1.cpp header_1.h header_2.h
So, in the linking step, I can immediately conclude that I will need to link together the files bin_1.o, header_1.o, and header_2.o in order to generate the binary bin_1. In other words, a corresponding dependency file for bin_1 should have
bin_1: bin_1.o header_1.o header_2.o
That is exactly what I have tried to achieve. The translation described above is done by a small python script, extract_dependencies.py, and a stripped-down version of my Makefile then looks like this:
binaries = bin_1 bin_2 bin_3
SRCS := $(wildcard *.cpp)
all: $(binaries)
# dependencies
DEPDIR := .d
$(shell mkdir -p $(DEPDIR) >/dev/null)
DEPFLAGS = -MT $# -MMD -MP -MF $(DEPDIR)/$*.Td
COMPILE = $(CC) $(DEPFLAGS) $(CFLAGS) -c
POSTCOMPILE = mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d
GENERATE_BINARY_DEPS = python extract_dependencies.py $(DEPDIR)/$*.d > $(DEPDIR)/$*.bin.d
$(DEPDIR)/%.d: ;
$(DEPDIR)/%.bin.d: ;
.PRECIOUS: $(DEPDIR)/%.d $(DEPDIR)/%.bin.d
$(binaries): % : %.o $(DEPDIR)/%.bin.d
${CC} ${CFLAGS} $(shell cat .d/$#.bin.d | cut -d ' ' -f 2-) ${LDFLAGS} -o $#
%.o: %.cpp
%.o: %.cpp $(DEPDIR)/%.d
$(COMPILE) $<
$(POSTCOMPILE)
$(GENERATE_BINARY_DEPS)
clean:
rm -vf *.o
rm -vf bin_1 bin_2 bin_3
realclean:
$(MAKE) clean
rm -fr .d
-include $(patsubst %,$(DEPDIR)/%.d,$(basename $(SRCS)))
-include $(patsubst %,$(DEPDIR)/%.bin.d,$(basename $(SRCS)))
Now comes the problem: in order for that to work, I need to run "make" twice. The *.bin.d dependency files are generated, but only on the second run, Make actually "realizes" that say header_1.o is also necessary for bin_1, not only bin_1.o. On the first run, it tries to link all the object files together without actually building all the object files first.
Is there any way to come around that issue, i. e. get everything right on the first pass?
Thanks!

Answer 1

Since Make will read-in whole makefile at 1st, then perform targets. It's hard to get %.bin.d updated in one pass. Alternatively, we could try to trigger 2nd "make" internally like,
ifneq ($(STAGE),2)
$(binaries): % : %.o $(DEPDIR)/%.bin.d
#{MAKE} $(binaries) STAGE=2
else
#2nd pass
$(binaries):
${CC} ${CFLAGS} -o $# $(shell cat .d/$#.bin.d | cut -d ' ' -f 2-) ${LDFLAGS}
endif