A 3 level comparator - compare

Question

I want to make a comparator with some tolerance.
I have taken the difference between the two signals (hopefully)
Now I want to compare to a number (which will be decided later) and respectively forward signals of equal notequal and acceptable.
I have let the commented portion to help you understand my approach.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity threelvlcomp is
port (
input1 : in std_logic_vector(15 downto 0);
input2 : in std_logic_vector(15 downto 0);
outputeq : out std_logic;
outputneq : out std_logic
);
end threelvlcomp;
architecture Behavioral of threelvlcomp is
signal temp : std_logic_vector(15 downto 0);
signal dif : std_logic_vector(15 downto 0);
--CONSTANT limit : INTEGER := 1;
begin
dif <= std_logic_vector(unsigned(input1)) + std_logic_vector(unsigned(not(input2) + 1));
--dif <= input1 + not(input2)+ "1";
--dif <= input1 + not(input2) + "1";
outputeq <= '1' when dif < '1' else
'0';
outputneq <= '1' when dif > '1' else
'0';
-- IF dif = "0000" THEN
-- outputeq <= '1';
-- outputneq <= '0';
-- outputacc <= '0';
--ELSE IF dif /= '0' THEN
-- outputeq <= '0';
-- outputneq <= '1';
--outputacc <= '0';
--ELSE IF dif <= "0.5";
-- outputeq <= '0';
-- outputneq <= '0';
-- outputacc <= '1';
--ELSE
-- outputeq <= '1';
-- outputneq <= '1';
-- outputacc <= '1';
--END IF;
-- If(dif = 0) then outputeq <='1'; else outputeq <= '0';end if;
-- If(dif >= -0.5 and dif <= 0.5) then outputacc <='1'; else outputacc <= '0';end if;
-- If(dif /= 0) then outputneq <='1' else outputneq <= '0';end if;
end Behavioral;

Answer 1

I have not tested this code. But to me looks like it is what you are trying to do. It should at least help you with your signed/unsigned issue.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all; --do not use this it is confusing you
entity threelvlcomp is
port (
input1 : in std_logic_vector(15 downto 0);
input2 : in std_logic_vector(15 downto 0);
outputeq : out std_logic;
outputneq : out std_logic
);
end threelvlcomp;
architecture Behavioral of threelvlcomp is
signal temp : unsigned(15 downto 0);
signal dif : signed(16 downto 0);
--CONSTANT limit : INTEGER := 1;
begin
-- you want a signed number here so we need to signed extend with a zero
dif <= (signed('0'input1)) + (not signed('0'&input2)) + 1;
--dif <= input1 + not(input2)+ "1";
--dif <= input1 + not(input2) + "1";
outputeq <= '1' when dif < 1 else
'0';
outputneq <= '1' when dif > 1 else
'0';
end Behavioral;