OpenOCD on Beaglebone Black - openocd

This is my first post ever on this board and I am also fairly new to the world of JTAG debugging, I have used a few commercial products before but I would like to make the switch to OpenOCD and I am experiencing a lot of failures so far. I have tried to attach to my Beaglebone Black using a Flyswatter2 and the kit that they provide and most of my results look something like this:
$ ./openocd -f interface/ftdi/flyswatter2.cfg -f
board/ti_beaglebone_with_fs2.cfg -c init -c "reset init"
Open On-Chip Debugger 0.10.0-dev-00149-g8229d52 (2015-12-23-11:37)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Warn : Interface already configured, ignoring
adapter speed: 16000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Warn : target name is deprecated use: 'cortex_a'
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
connect_deassert_srst
Info : clock speed 16000 kHz
Info : JTAG tap: am335x.jrc tap/device found: 0x2b94402f (mfg: 0x017,
part: 0xb944, ver: 0x2)
Info : JTAG tap: am335x.dap enabled
Warn : Timeout (1000ms) waiting for ACK=OK/FAULT in JTAG-DP transaction
- aborting
Info : JTAG tap: am335x.jrc tap/device found: 0x2b94402f (mfg: 0x017,
part: 0xb944, ver: 0x2)
Info : JTAG tap: am335x.dap enabled
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed
Error: MEM_AP_CSW 0x2800060, MEM_AP_TAR 0x0
Error: Target not examined yet
in procedure 'reset'
in procedure 'ocd_bouncer'
I have tried to reduce the adapter speed with some success, where the device actually reboots but all hell breaks loose once the kernel starts at which point I get error messages similar to the ones above.
I am not really sure where to start as those error messages are still a little obscure to me, would anyone have any ideas/thoughts/suggestions? I'd be willing to dig in the source and make some adjustments if need be, but right now I'm a little bit too clueless to do so!

Well, just since I can't seem to find any other post that shows ppl succesfully debugging the BeableBone Black with openocd, I can vouch for the fact that it works. My commandline (using the TIAO):
sudo ../src/openocd -f interface/ftdi/tumpa.cfg -f board/mybbb.cfg
Note that the paths come from the fact that I built it and ran it from source (you might need other path prefixes). The mybbb.cfg is basically the one from flyswatter, except the interface line. (https://www.tincantools.com/w/images/f/f7/ti_beaglebone_with_fs2.cfg)
Openocd can be a bit hard to use, but it does forces you to understand what really is happening with the JTAG. If you won't want to, just buy the 80$ connector from TI, and it will -just- work (provided that you get the pinheader soldered on it correctly)
FYI: The succesful output in my case (useful to diff):
testbox#testbox-VirtualBox:~/openocd/openocd-code/tcl$ sudo ../src/openocd -f interface/ftdi/tumpa.cfg -f board/ti_beaglebone.cfg
Open On-Chip Debugger 0.10.0-dev-00322-g406f4d1 (2016-06-09-09:22)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 16000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
trst_and_srst separate srst_gates_jtag trst_push_pull srst_push_pull connect_deassert_srst
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 16000 kHz
Info : JTAG tap: am335x.jrc tap/device found: 0x2b94402f (mfg: 0x017 (Texas Instruments), part: 0xb944, ver: 0x2)
Info : JTAG tap: am335x.dap enabled
Info : am335x.cpu: hardware has 6 breakpoints, 2 watchpoints
Finally, regarding your errors, I would double check the solder, since openocd really is saying your clock might be too fast. Fast clocking with small leakage might explain your issue?
One last thing to note:
If you want to debug the linux kernel with JAG on the beaglebone on a recent kernel, you might need a patch. If not, you will get errors in openocd (but also with the dongles from TI) once linux boots since it messes up the JTAG. See the 1-line patch in https://e2e.ti.com/support/embedded/linux/f/354/t/363421 (took me a while to find!)
Good luck!

Be sure that your config file is providing the good ID Vendor and ID product of your target. The command lsusb give you your target IDs.

Related

Load failed. Load program to AM243x Launchpad

enter image description here
I try to load the program to AM243x Launchpad and it has this issue on the console window:
MAIN_Cortex_R5_0_0: GEL Output: CPU reset (soft reset) has been issued through GEL.
MAIN_Cortex_R5_0_0: Trouble Writing Memory Block at 0x0 on Page 0 of Length 0x40: (Error -1065 # 0x40) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.8.0.00235)
MAIN_Cortex_R5_0_0: File Loader: Verification failed: Target failed to write 0x00000000
MAIN_Cortex_R5_0_0: GEL: File: D:\Documents\CCS\hello_world_haha\Debug\hello_world_haha.out: Load failed.

STM32cubeide with stm32f103c8t6 could not verify ST device

I am new to embedded and stm32cubeide, self teaching so I can use it in a group project related to university studies.
After purchasing a "blue pill" from aliexpress, I realized I might of bought a clone chip. I followed the instructions shown here (stm32 community site), and I'm still getting an error that the ide cannot verify my ST device.
Here is what I have as output:
Open On-Chip Debugger 0.11.0+dev-00443-gcf12591 (2022-02-09-13:33) [ST Internal]
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
swv
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : STLINK V2J39S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.286227
Info : clock speed 4000 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x2ba01477
Info : STM32F103C8Tx.cpu: Cortex-M3 r2p1 processor detected
Info : STM32F103C8Tx.cpu: target has 6 breakpoints, 4 watchpoints
Info : starting gdb server for STM32F103C8Tx.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
Info : device id = 0x20036410
Info : flash size = 128kbytes
Warn : GDB connection 1 on target STM32F103C8Tx.cpu not halted
undefined debug reason 8 - target needs reset
O.K.
O.K.:0xE00FFFD0
Info : dropped 'gdb' connection
shutdown command invoked
I see in the console "undefined debug reason 8 - target needs reset", is this the problem? If so what can I do to solve this? If not, then what do I do other than purchasing another board?
Below is my test Debug.cfg, in case I need to change something in there:
# This is an genericBoard board with a single STM32F103C8Tx chip
#
# Generated by STM32CubeIDE
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
source [find interface/stlink-dap.cfg]
set WORKAREASIZE 0x5000
transport select "dapdirect_swd"
set CHIPNAME STM32F103C8Tx
set BOARDNAME genericBoard
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# STlink Debug clock frequency
set CLOCK_FREQ 4000
# Reset configuration
# use software system reset if reset done
reset_config none
set CONNECT_UNDER_RESET 0
set CORE_RESET 0
# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 3333
# BCTM CPU variables
source [find target/stm32f1x.cfg]
# SWV trace
set USE_SWO 0
set swv_cmd "-protocol uart -output :3344 -traceclk 16000000"
source [find board/swv.tcl]
Thanks
I found some FT232 that I had in spare, and I was able to program the chip using the stm32 programmer software and a generated hex file from the ide.
I'll use this method if ever I run into cloned chips and the st link v2 if ever I get a genuine board.

Cyclone V soc - problem with debugging app from SDRAM

I've encountered a problem with debugging bare-metal app on Terasic DE-10 Standard board.
I'm using Quartus Prime 20.1 Lite Edition, SoC EDS 20.1. I'm working with eclipse 2021-06, openocd 0.10.0 (installed with apt - it was not compiled on my host Ubuntu 18) and with gnu linaro toolchain 2019.12 version which comes with SoC EDS.
The problem is that I can't debug app which runs from SDRAM while I don't have any problem with launching it from on-chip RAM). GDB halts on entry point, but CPU resets when I run the app. I can observe this behavior when I power the board, I stop U-Boot just before it tries to perform autoboot command, and then I try to launch app via GDB. However, when I launch app from U-Boot console ( loading binary from SD card ) it works fine and then I can launch the app via GDB and debug it successfully. When I modify the app, then I have to repeat the procedure in order that I can debug it (run from U-Boot, then launch with openocd).
I am using Altera-SoCFPGA-HardwareLib-Timer-CV-GNU example and openocd configs shown below.
altera-usb-blaster2.cfg:
#
# Altera USB-Blaster II
#
interface usb_blaster
usb_blaster_vid_pid 0x09fb 0x6010 0x09fb 0x6810
usb_blaster_lowlevel_driver ublast2
usb_blaster_firmware /home/jakub/intelFPGA_lite/20.1/quartus/linux64/blaster_6810.hex
altera_sockit.cfg:
#
# Cyclone V SocKit board
# http://www.altera.com/b/arrow-sockit.html
#
# Software support page:
# http://www.rocketboards.org/
source [find interface/altera-usb-blaster2.cfg]
source [find target/altera_fpgasoc.cfg]
altera_fpgasoc.cfg:
#
# Altera cyclone V SoC family, 5Cxxx
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME fpgasoc
}
# Subsidiary TAP: fpga
if { [info exists FPGA_TAPID] } {
set _FPGA_TAPID $FPGA_TAPID
} else {
set _FPGA_TAPID 0x02d020dd
}
jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
#
# Cortex-A9 target
#
# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0 - 0x80110000
# core 1 - 0x80112000
# Slow speed to be sure it will work
adapter_khz 1000
set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1
# A9 core 0
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
$_TARGETNAME1 configure -event gdb-attach { halt }
# A9 core 1
# target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
# $_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
# $_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
# $_TARGETNAME2 configure -event gdb-attach { halt }
proc cycv_dbginit {target} {
# General Cortex-A8/A9 debug initialisation
cortex_a dbginit
}
I run debugger with "openocd -f board/altera_sockit.cfg"
Logs from console until halting on entry:
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
cycv_dbginit
Started by GNU MCU Eclipse
Info : Altera USB-Blaster II found (Firm. rev. = 1.39)
Info : This adapter doesn't support configurable speed
Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0)
Info : JTAG tap: fpgasoc.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints
Info : accepting 'gdb' connection on tcp/3333
Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41
Info : fpgasoc.cpu.0 cluster 0 core 0 multi core
target halted in Thumb state due to debug-request, current mode: Supervisor
cpsr: 0x000001f3 pc: 0x3ff92798
MMU: enabled, D-Cache: enabled, I-Cache: enabled
Error: Translation from khz to jtag_speed not implemented
in procedure 'reset'
in procedure 'ocd_bouncer'
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 248
in procedure 'fpgasoc.cpu.0' called at file "embedded:startup.tcl", line 286
in procedure 'ocd_bouncer'
Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0)
Info : JTAG tap: fpgasoc.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Error: fpgasoc.cpu.0: how to reset?
in procedure 'reset'
in procedure 'ocd_bouncer'
semihosting is enabled
Info : DAP transaction stalled (WAIT) - slowing down
Error: Translation from khz to jtag_speed not implemented
in procedure 'reset'
in procedure 'ocd_bouncer'
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 248
in procedure 'fpgasoc.cpu.0' called at file "embedded:startup.tcl", line 286
in procedure 'ocd_bouncer'
Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0)
Info : JTAG tap: fpgasoc.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Error: fpgasoc.cpu.0: how to reset?
in procedure 'reset'
in procedure 'ocd_bouncer'
Warn : negative acknowledgment, but no packet pending
Info : DAP transaction stalled (WAIT) - slowing down
===== ARM registers
(0) r0 (/32): 0x3BF65CE0 (dirty)
(1) r1 (/32): 0x00000014 (dirty)
(2) r2 (/32): 0x00000076
(3) r3 (/32): 0x3FF7E2C7
(4) r4 (/32): 0x00000000
(5) r5 (/32): 0x3FFEAA10
(6) r6 (/32): 0x3FFCA614
(7) r7 (/32): 0x3FFE0E4C
(8) r8 (/32): 0x00000000
(9) r9 (/32): 0x3BF64EE0
(10) r10 (/32): 0x00000001
(11) r11 (/32): 0x00000017
(12) r12 (/32): 0x3FFE4E50
(13) sp_usr (/32)
(14) lr_usr (/32)
(15) pc (/32): 0x00100060 (dirty)
(16) r8_fiq (/32)
(17) r9_fiq (/32)
(18) r10_fiq (/32)
(19) r11_fiq (/32)
(20) r12_fiq (/32)
(21) sp_fiq (/32)
(22) lr_fiq (/32)
(23) sp_irq (/32)
(24) lr_irq (/32)
(25) sp_svc (/32): 0x3BF5FEE8
(26) lr_svc (/32): 0x3FF7B07F
(27) sp_abt (/32)
(28) lr_abt (/32)
(29) sp_und (/32)
(30) lr_und (/32)
(31) cpsr (/32): 0x000001D3 (dirty)
(32) spsr_fiq (/32)
(33) spsr_irq (/32)
(34) spsr_svc (/32): 0x0C02AB02
(35) spsr_abt (/32)
(36) spsr_und (/32)
(37) sp (/32)
(38) lr (/32)
(39) sp_mon (/32)
(40) lr_mon (/32)
(41) spsr_mon (/32)
After running the debugger (cpu resets):
Error: Debug regions are unpowered, an unexpected reset might have happened
Error: JTAG-DP STICKY ERROR
Warn : target fpgasoc.cpu.0 is not halted
Polling target fpgasoc.cpu.0 failed, trying to reexamine
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: Target not halted
Error: cortex_a_mmu: target not halted
Warn : target not halted
Error: cortex_a_mmu: target not halted
Warn : target not halted
Error: Invalid ACK (6) in DAP response
Polling target fpgasoc.cpu.0 failed, trying to reexamine
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints
Error: Invalid ACK (6) in DAP response
Polling target fpgasoc.cpu.0 failed, trying to reexamine
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : DAP transaction stalled (WAIT) - slowing down
Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints
Info : dropped 'gdb' connection
I hope someone can help me.
I've probably found the solution/workaround, which is to disable cache from U-Boot console: icache off and dcache off, although it causes that CPU frequency slows down. If someone could explain in detail this behavior, I would be thankful.

ocd assertion fault when connecting gdb

I am debugging board STM32f4 Discovery on Ubuntu 20.04 with openocd and arm-none-eabi-none. Things work well until yesterday. Today, when I connect the gdb to localhost:4444, following assertion happened and ocd quit:
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 2000 kHz
adapter_nsrst_delay: 100
none separate
srst_only separate srst_nogate srst_open_drain connect_deassert_srst
Started by GNU MCU Eclipse
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2 JTAG v37 API v2 SWIM v26 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 2.894743
Info : stm32f4x.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : accepting 'gdb' connection on tcp/3333
Info : device id = 0x100f6413
Info : flash size = 8194kbytes
openocd: src/flash/nor/stm32f2x.c:990: stm32x_probe: Assertion `(bank->size >> 10) == flash_size_in_kb' failed.
I see that it is using stm32f2x.c, is it correct since the chip is stm32f407vgt?
I found the issue: I scale up the clock speed without switching to appropriate Flash Latency so the debugger will lose the track of program address as mentioned here, in Clocks and initial settings part:
https://vjordan.info/log/fpga/first-steps-with-the-stm32f4.html

HP ProLiant 100 G5/G6/G7 Servers Series - Showing Uncorrectable ECC Events Occurred in SEL Log

HP Insight Diagnostics Version 8.4.0.3521A (x86_64)
Computer Name: ezsetupsystem3c4a927c9e88
During Device test it gives following error
Total Memory-ECC test Failed
Description- Uncorrectable ECC Events occurred in SEL log Device, Ran on CPU 0
Recommended Repair- Please refer IPMI Sensor Event Log for ECC events
Error Code- 021278
Please help me n finding why is this error coming.
Is it because of WAMP server installation??
This means that the server has a DIMM which has exceeded it's acceptable ECC error count. It's location is denoted in the error. Depending on the platform, you can identify the specific slot. Which HP ProLiant model is this? This is standard warranty repair.
You have faulty memory. To identify the faulty memory run HPS Reports:
http://update.external.hp.com/HPS/HPSreports/
Once completed you have to unzip the archive an open the index.html file insite.
It will collect all hardware information and highlight in
RED
the faulty components.