Below is a makefile. Please refer to the section where %.c is the target, and one of the dependencies is a .psvn file. I would like this make file to go through every psvn file and generate a .c file for it. How would I change the makefile to do this?
CC = gcc
CXX = g++
OPT = -g -Wall -O3 -Wno-unused-function -Wno-unused-variable -std=c++11
PSVNOPT = --no_state_map --no_abstraction --backwards_moves --history_len=0
psvn2c_core.c:
cp ../psvn2c_core.c ./psvn2c_core.c
psvn2c_state_map.c:
cp ../psvn2c_state_map.c ./psvn2c_state_map.c
psvn2c_abstraction.c:
cp ../psvn2c_abstraction.c ./psvn2c_abstraction.c
%.c: %.psvn psvn2c_core.c psvn2c_state_map.c psvn2c_abstraction.c
../psvn2c $(PSVNOPT) --name=$(*F) < $< > $#
rm -f ./psvn2c_core.c ./psvn2c_state_map.c ./psvn2c_abstraction.c
.PRECIOUS: %.c
%.succ: %.c succ.c
$(CC) $(OPT) succ.c -include $< -o $#
%.run: %.c run.cpp Node.cpp distribution.cpp
$(CXX) $(OPT) run.cpp Node.cpp distribution.cpp -include $< -o $#
.PHONY : clean
clean:
rm -f *.run *.o psvn2c_core.c psvn2c_state_map.c psvn2c_abstraction.c
Add something like this BEFORE the first target (psvn2c_core.c:):
PSVN_FILES := $(wildcard *.psvn)
C_FILES := $(patsubst %.psvn,%.c,$(PSVN_FILES))
all: $(C_FILES)
Done. When make all (or make since all will be the default target since it appears first in the makefile) is invoked, it will try to build all the .c files.
Related
I am trying to write a make file for the following program
MY file/folder structure is as follows
Folder/File structure
./demo/utilities.c
./demo/utilities.h
./demo/makefile
./include/GeographicLib/UTMUPS.h
./include/GeographicLib/Constant.h
./include/GeographicLib/xxxxxxx
in the file utilities.h
#include <GeographicLib/UTMUPS.h>
in the file UTMUPS.h
#include <GeographicLib/Constant.h>
in the makefile
# preprocessor
PREPROC_FLAGS += -DEIGEN_DONT_ALIGN_STATICALLY
INC_XTRA_DIR = ../include
CC=g++
CPPFLAGS= $(PREPROC_FLAGS)
CFLAGS=-O2 -g -Wall -W -I$(INC_XTRA_DIR)
CXXFLAGS=-O2 -g -Wall -W -fpic -std=c++11
# short hand
OBJDIR=obj
Utilities_h = utilities.h GeographicLib/UTMUPS.hpp
utilities.o: utilities.c $(Utilities_h)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
all: $(FINAL_TARGET)
$(FINAL_TARGET): $(OBJ)
$(CC) -g -o $# $^ $(LDFLAGS)
ifneq ($(wildcard ../databases/.),)
cp $# ../
endif
TargetList = $(FINAL_TARGET)
clean:
rm -f $(TargetList) *.o *~
echo Clean done.
The question I want to ask is
When I compile the following project, it say it can't find "#include 'GeographicLib/UTMUPS.h'". in the utilities.h. what should the naming be in this case. My thought is that by adding -I$(INC_XTRA_DIR), or ../include ... it should search for GeographicLib/UTMUPS.h
what about the file that UTMUPS.h is dependent on(in this case Constant.h), what should be the addressing
Edit: I run make at the root directory... maybe that's the reason for the error.
THanks
GNU Make 3.82
gcc 4.7.2
c89
I have the following make file:
INC_PATH=-I/home/dev_tools/apr/include/apr-1
LIB_PATH=-L/home/dev_tools/apr/lib
LIBS=-lapr-1 -laprutil-1
RUNTIME_PATH=-Wl,-rpath,/home/dev_tools/apr/lib
CC=gcc
CFLAGS=-Wall -Wextra -g -m32 -O2 -D_DEBUG -D_THREAD_SAFE -D_REENTRANT -D_LARGEFILE64_SOURCE $(INC_PATH)
SOURCES=$(wildcard src/*.c)
OBJECTS=$(patsubst %.c, %.o, $(SOURCES))
EXECUTABLE=bin/to
all: build $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(CFLAGS) -o $# $(RUNTIME_PATH) $(OBJECTS) $(LIB_PATH) $(LIBS)
$(OBJECTS): $(SOURCES)
$(CC) $(CFLAGS) -c $(SOURCES) $(LIB_PATH) $(LIBS)
build:
#mkdir -p bin
clean:
rm -rf $(EXECUTABLE) $(OBJECTS) bin
find . -name "*~" -exec rm {} \;
find . -name "*.o" -exec rm {} \;
My directory structure is like this project/src project/bin. My Makefile is in the project (root) folder, and all my *.h and *.c are in the src directory. Currently I have only one source file called timeout.c
I get this error:
gcc: error: src/timeout.o: No such file or directory
I have used this to get all the source files:
SOURCES=$(wildcard src/*.c)
And the object files:
OBJECTS=$(patsubst %.c, %.o, $(SOURCES))
However, the make seems to create the object file in the project root folder where the Makefile is. Should it not put it in the src directory?
You have two problems in this rule (well, three):
$(OBJECTS): $(SOURCES)
$(CC) $(CFLAGS) -c $(SOURCES) $(LIB_PATH) $(LIBS)
You haven't noticed yet, but the rule makes each object dependent on all sources, and tries to build that way. Not a problem as long as you have only one source. Easy to fix with a static pattern rule and an automatic variable:
$(OBJECTS): src/%.o : src/%.c
$(CC) $(CFLAGS) -c $< $(LIB_PATH) $(LIBS)
Also, the command ("$(CC)...") doesn't specify an output file name, so gcc will infer it from the source file name; if you give it src/timeout.c, it will produce timeout.o (in the working directory, project/). So you should specify the desired path to the output file. Easy to do with another automatic variable:
$(OBJECTS): src/%.o : src/%.c
$(CC) $(CFLAGS) -c $< $(LIB_PATH) $(LIBS) -o $#
Use gcc's -o option to write the output file to a particular location. For instance, you could say:
$(CC) $(CFLAGS) -c $(SOURCES) $(LIB_PATH) $(LIBS) -o $(OBJECTS)
Unfortunately, there's a problem with this line: if there is more than one source file in $(SOURCES), it won't work, since $(OBJECTS) will also contain multiple file names, and the -o option only binds to the first argument.
A way to compile each file in a list of source code files is to use implicit rules. In gmake, you would write:
$(EXECUTABLE): $(OBJECTS)
$(CC) $(CFLAGS) -o $# $(RUNTIME_PATH) $(OBJECTS) $(LIB_PATH) $(LIBS)
%.o : %.c
$(CC) $(CFLAGS) -c $< -o $#
where $< is replaced with name of the input file and $# is replaced with the name out the output file.
I solved this request and here is my Makefile and directory tree.
PROJECT := main.exe
DIR_SRC += .
DIR_SRC += ./src
DIR_INC += -lpthread
DIR_INC += -I./inc
DIR_INC += $(addprefix -I, $(DIR_SRC))
SRC_C += $(wildcard $(addsuffix /*.c, $(DIR_SRC)))
#OBJ := $(filter %.o, $(SRC_C:.c=.o))
OBJ := $(patsubst %.c, %.o, $(SRC_C))
EXE := $(PROJECT)
CC_PREFIX :=
CC := $(CC_PREFIX)gcc
CFLAG =
CLIB = -L .
.PHONY:all
all:$(OBJ) $(EXE)
%.o: %.c
$(CC) $(CFLAG) $(DIR_INC) -c $< -o $#
$(EXE): $(OBJ)
$(CC) $(CFLAG) $(CLIB) $(OBJ) -o $#
clean:
rm -r $(EXE) $(OBJ)
See my directory tree:
I have a makefile where I am working with both C source and CPP source. Below is a snippet of code from the makefile. Is there a way to combine the following two targets to compile both filetypes?
#definitions
OBJ_DIR := obj
DEP_DIR := dep
CXX := g++
DEBUG := -g -O0
OPT := -std=c++11 -Wextra -Wall -pthread
LFLAGS = $(DEBUG) $(OPT) $(INC)
CFLAGS = $(LFLAGS) -c
#auto-dependency generation (part 1)
DEP_FLAGS = -MT $# -MMD -MP -MF $(DEP_DIR)/$*.Td
POSTCOMPILE = #mv -f $(DEP_DIR)/$*.Td $(DEP_DIR)/$*.d && touch $#
#compile object files from CPP source
$(OBJ_DIR)/%.o: %.cpp $(DEP_DIR)/%.d
$(CXX) $(CFLAGS) $(DEP_FLAGS) $< -o $#
$(POSTCOMPILE)
#compile object files from C source
$(OBJ_DIR)/%.o: %.c $(DEP_DIR)/%.d
$(CXX) $(CFLAGS) $(DEP_FLAGS) $< -o $#
$(POSTCOMPILE)
#auto-dependency generation (part 2)
$(DEP_DIR)/%.d: ;
.PRECIOUS: $(DEP_DIR)/%.d
include $(wildcard $(DEP_DIR)/*.d)
I have tried to use the wildcard function with a variety of different formatting using second expansion but to no avail.
I am using Make 4.2. The auto-dependency generation code was taken from http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/.
Thanks in advance
Using the right variables as well as the define, call and eval features, the following is possible:
EXT := c cpp
define rule =
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.$(1)
$$(COMPILE.$(1)) $$< -o $$#
endef
$(foreach ext, $(EXT), $(eval $(call rule,$(ext)))) # NO SPACE before $(ext)!!!
make has implicit variables and rules, especially many COMPILE.* rules (you can see them all by issuing the shell command make -p | grep 'COMPILE.* ='):
COMPILE.c = $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
COMPILE.cpp = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
CPPFLAGS is used for preprocessor flags (cpp is the preprocessor executable in the GNU GCC toolchain). TARGET_ARCH is empty on most platforms by default.
Here is a full yet minimalist working Makefile with better auto-dependency generation (note that putting the .d files in a folder separate from the .o pointlessly complicates the makefile):
TARGET := executable
EXT := c cpp
SRC_DIR := .
OBJ_DIR := obj
DEP_DIR := dep
CPPFLAGS = -MMD -MP -MF $(#:$(OBJ_DIR)/%.o=$(DEP_DIR)/%.d)
CFLAGS := -Wall -Wextra -pthread
CXXFLAGS := -std=c++11 $(CFLAGS)
LDFLAGS := -pthread
SOURCE := $(foreach ext, $(EXT), $(wildcard $(SRC_DIR)/*.$(ext)))
OBJECT := $(SOURCE:$(SRC_DIR)/%=$(OBJ_DIR)/%.o)
DEPEND := $(OBJECT:$(OBJ_DIR)/%.o=$(DEP_DIR)/%.d)
define rule =
$(OBJ_DIR)/%.$(1).o: $(SRC_DIR)/%.$(1) | $(OBJ_DIR) $(DEP_DIR)
$$(COMPILE.$(1)) $$< -o $$#
endef
.PHONY: all clean
all: $(TARGET)
$(TARGET): $(OBJECT)
$(CXX) $(LDFLAGS) $^ -o $#
$(foreach ext, $(EXT), $(eval $(call rule,$(ext))))
$(OBJ_DIR) $(DEP_DIR):
mkdir -p $#
-include $(DEPEND)
clean:
$(RM) -r $(TARGET) $(OBJ_DIR) $(DEP_DIR)
Also note that I chose to add the original source file extension (c or cpp) to the object file name (.c.o or .cpp.o) to tackle the case where we could encounter source files with different extension but with the same name.
I have a problem with the dependencies in my Makefile.
There is no problem with the compilation, it compiles perfectly the good *.cc and *.hh but unfortunately, it does not re-compile the dependencies, thus there is no update in the executable.
Here is my makefile:
EXEC ?= program
SRCS = $(shell find -name *.cc)
DEP = $(SRCS:.cc=.d)
OBJDIR = objs
OBJS = $(SRCS:./%.cc=$(OBJDIR)/%.o)
CXX = g++
CFLAGS = -std=c++14 $(addprefix "-I", $(shell find -type d))
## Clean rule
.PHONY: clean
clean:
rm -rf $(OBJDIR)
rm -f $(EXEC)
$(EXEC) : $(OBJS)
#echo "Linking: $#"
$(CXX) $(OBJS) -o $#
-include $(DEP)
$(OBJDIR)/%.o : ./%.cc ./%.hh
#mkdir -p $(#D)
#echo "Compiling: $<"
#$(CXX) -c $(CFLAGS) -MT $# -MMD -MP -o $# $<
It is probably something related to the flag used by g++ but I do not manage to find the solution;
Thanks in advance for the help that you can provide on this issue,
If you do not specify the filename for the generated dependency files, it is going to be ${#:%.o=%.d} (compiler logic). I.e. your dependency files are in $(OBJDIR) and not in ./ where your makefile expects them to be.
Two alternative solutions:
DEP := $(OBJS:%.o=%.d).
#$(CXX) -c $(CFLAGS) -MT $# -MMD -MP -MF $(<:%.cc=%.d) -o $# $<
Consider the following Makefile:
# <include global configuration Makefile>
INCL = -I../include \
-I<whatever>
CPPFLAGS=$(DEFS) $(INCL)
CXXFLAGS = -O0 -g -Wall -fmessage-length=0
SRCS = $(wildcard *.cpp)
OBJS = $(SRCS:.cpp=.o)
all: $(OBJS)
%.o: %.cpp
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $# $<
depend: .depend
.depend: $(SRCS)
$(CPP) $(CPPFLAGS) -M $^ > $#
clean:
rm -f $(OBJS)
rm .depend
-include .depend
This Makefile creates an #include dependency chain using the g++ -M command, and includes it. This can be a rather long process. The problem is that this file is generated even if make clean is called, when this file would be deleted anyway. Is ther a way to conditionally include this file, and not bother creating it if the clean target is run?
Something like this:
ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif
See the make manual page on Goals for more information
Edit: -include cannot be tab indented, otherwise it is ignored.
You can do such dependencies for free (i.e., at no runtime cost) during the compile. When you run clean, the dependencies are naturally not remade. See the section Combining Compilation and Dependency Generation in Paul Smith's Advanced Auto-Dependency Generation paper.