Compile and link sources from different directories with make and gcc - c++

Question

I`m having a Project with some subdirectories. I want to compile them with one makefile per Directory and link all Output files into one executable. Can anyone explain me, which commands I should use (-c or -g or extra call)?
makefile in my root-directory:
LIBS =
# The test will be called in this file. There is no need to change this.
#SRCS = main_test.c
SRCS = min.c max.c
###############################################################################
# #
# Normally it is not needed to edited below this. #
# #
###############################################################################
#SRCS = main_test.c Automated.c Basic.c Console.c CUCurses.c CUError.c Cunit_intl.c \
# MyMem.c TestDB.c TestRun.c Util.c wxWidget.c main_test.c \
# $(TST_SRCS)
# define the C object files
#
# This uses Suffix Replacement within a macro:
# $(name:string1=string2)
# For each word in 'name' replace 'string1' with 'string2'
OBJ = $(SRCS:%.c=%.o)
# define the C compiler to use
CC = gcc
# define any compile-time flags
ODIR = out
#compile and link
#CFLAGS = -O0 -g -Wall -fmessage-length=0 -fprofile-arcs -ftest-coverage
#compile without link
CFLAGS = -O0 -c -Wall -fmessage-length=0 -fprofile-arcs -ftest-coverage
#TODO Linkerflags
LFLAGS = --coverage
#VPATH=test
#VPATH=source
# define the executable file,
TARGET = CUnit
export COVERAGE = $(TST_SRCS)
export STUBS = $(STUB_SRCS)
all:
$(MAKE) -C stub
$(MAKE) -C source
#echo --- build finished ---
#echo.
#echo TODO
#echo --- start linking ---
#echo.
and makefile of subdirectory
# define any directories containing header files other than /usr/include
# TODO
# define any libraries to link into executable:
# if I want to link in libraries (libx.so or libx.a) I use the -llibname
# option, something like (this will link in libmylib.so and libm.so:
LIBS =
# TODO define the C source files
SRCS = $(COVERAGE)
# define the C object files
#
# This uses Suffix Replacement within a macro:
# $(name:string1=string2)
# For each word in 'name' replace 'string1' with 'string2'
OBJ = $(SRCS:%.c=%.o)
# define the C compiler to use
CC = gcc
# define any compile-time flags
ODIR = ../out
#compile without link
CFLAGS = -O0 -c -fmessage-length=0 -fprofile-arcs -ftest-coverage
#TODO Linkerflags
LFLAGS = --coverage
# define the executable file,
all: $(TARGET) $(OBJ)
$(CC) $(OBJ) $(CFLAGS) -o $(TARGET) $(LFLAGS) $(OBJ)
#echo +++ build of source finished +++
clean:
$(RM) *.o *~ $(MAIN)
# DO NOT DELETE THIS LINE -- make depend needs it
I it is easier for the linker, if all Output file are in the same Directory. Works this with ODIR?

Answer 1

With the compiler option -c -g I can compile each submake and link the object files together.
CFLAGS = -O0 -Wall -c -g -fmessage-length=0 -fprofile-arcs -ftest-coverage