unit automat:the following signal(s) form a combinatorial loop - unit-testing

Question

I have some problems with this unit and I don't know why it's not working. The platform ISE Project Navigator gives me this error: unit automat:the following signal(s) form a combinatorial loop.I would like to receive some advice and if you can tell me how to resolve this problem.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity automat is
port(CLK,EN,SEN,MONED:in STD_LOGIC;
COMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
REN,MEN,ENR,IM_REST,REST,BILET,CLK_EN,RESET: out STD_LOGIC;
S1,S2,com:out STD_LOGIC_VECTOR(1 downto 0)
);
end automat;
architecture arh_automat of automat is
type STARE is(A,B,C,D,E,F,G,H,I,J);
signal ST,NXST:STARE;
begin
tranzitie:process(CLK,ST,EN,SEN,MONED,COMP)
begin
REN<='0';MEN<='0';clk_en<='0';RESET<='0';
ENR<='0';IM_REST<='0';REST<='0';BILET<='0';
S1<="00";S2<="00";com<="00";
case ST is
when A=>NXST<=B;
com<="00";
if(CLK'EVENT and CLK='1') then
if EN='1' then
ST<=B;
else
ST<=A;
end if;
END IF;
when B=>NXST<=C ;
RESET<='1';
com<="01";
if(CLK'EVENT and CLK='1') then
if EN='1' then
ST<=C;
else
ST<=B;
end if;
end if;
when C=>NXST<=D;
REN<='1';
CLK_EN<='1';
com<="10";
if(CLK'EVENT and CLK='1') then
if SEN ='1' then
ST<=D;
else
ST<=C;
end if;
end if;
when D=>NXST<=E ;
s1<="01";
s2<="10";
com<="10";
if(CLK'EVENT and CLK='1') then
if MONED='1' then
ST<=E;
else
ST<=F;
end if;
end if;
when E=>NXST<=F;
com<="00";
if(CLK'EVENT and CLK='1') then
ST<=F;
end if;
when F=>NXST<=G ;
MEN<='1';
com<="00";
if(CLK'EVENT and CLK='1') then
if COMP="010" or COMP="100" then
ST<=G;
else
ST<=C;
end if;
end if;
when G=>NXST<=H;
ENR<='1';
S1<="00";
S2<="11";
com<="00";
if(CLK'EVENT and CLK='1') then
if COMP="100" OR COMP="001" OR COMP="010" then
ST<=H;
else
ST<=I;
end if;
END IF;
when H=>NXST<=J;
REST<='1';
BILET<='1';
com<="00";
if(CLK'EVENT and CLK='1') then
ST<=J;
end if;
when I=>NXST<=J;
IM_REST<='1';
BILET<='1';
com<="00";
if(CLK'EVENT and CLK='1') then
ST<=J;
end if;
when J=>NXST<=A;
com<="00";
if(CLK'EVENT and CLK='1') then
ST<=A;
end if;
end case;
end process tranzitie;
end arh_automat;

Answer 1

You don't say which signals are forming the loop but your process & case construct are not written well.
Try splitting the combinatorial and synchronous signals into separate processes. Your clocking is messed up too. In the syncronous process, use just one "CLK'EVENT and CLK = '1'" statement with the case statement under it.

Answer 2

A combinatorial loop is when you have the output of some combinatorial logic fed back into itself. The most basic example I can think of is:
My_PROC : process(A)
begin
A <= not A;
end process;
Its obviously not possible to synthesize this.
Its pretty difficult to figure out what's going on in your code but you need to look for a case where the output of some combinatorial logic is fed back into itself. Like #lsf_design said, you should split up the combinatorial and clock synchronous logic. I would recommend using the format described here.
I would try to give your signals more descriptive names. Instead of using A, B, C, etc. for your state names, name them something that actually describes what that case does.