I am trying to test a source code and a header file (for mac layer) that is already exists in mixim. I just copied the (.cc) and (.h) files from scr folder in mixim and I have paste it in my project folder. and I also referred to the class in the (.NED) file of the mac layer. Unfortunately, I keep getting the same errors every time I tried to build the project. The errors are as follows:
Description Resource Path Location Type
make: *** [out/gcc-debug//WLAN_CSMA_test2.exe] Error 1 WLAN_CSMA_test2 C/C++ Problem
recipe for target 'out/gcc-debug//WLAN_CSMA_test2.exe' failed Makefile /WLAN_CSMA_test2 line 107 C/C++ Problem
A shot from the makefile (line 107 is bold):
####(#Main target
all: $O/$(TARGET)
$(Q)$(LN) $O/$(TARGET) .
$O/$(TARGET): $(OBJS) $(wildcard $(EXTRA_OBJS)) Makefile
**#$(MKPATH) $O**
#echo Creating executable: $#
$(Q)$(CXX) $(LDFLAGS) -o $O/$(TARGET) $(OBJS) $(EXTRA_OBJS) $(AS_NEEDED_OFF) $(WHOLE_ARCHIVE_ON) $(LIBS) $(WHOLE_ARCHIVE_OFF) $(OMNETPP_LIBS)
.PHONY: all clean cleanall depend msgheaders
.SUFFIXES: .cc
How can I fix this? Is there any other way that I can use to test the built-in source codes?
Thank you in advance.
Ohood.
Related
I have a makefile to generate some headers and cpp files from a yaml file.
../api/%.h ../api/%.cpp : ../idl/%.yml
$(info Generating api files from $<)
$(IDL_TO_CPP_EXE) --input $< --output $(basename $#)
IDL_HEADERS=$(IDL_INPUTS:../idl/%.yml=../api/%.h)
IDL_CPPS=$(IDL_INPUTS:../idl/%.yml=../api/%.cpp)
all: $(IDL_HEADERS) $(IDL_CPPS)
$(info The dependencies are $(IDL_HEADERS) $(IDL_CPPS))
IDL_INPUTS +=../idl/common_api/CommonTypes.yml
When I run it, it outputs the following, but without generating the .h and .cpp file. I've checked they aren't there, so it's not a timestamp issue.
The dependencies are ../api/common_api/CommonTypes.h ../api/common_api/CommonTypes.cpp
make: Nothing to be done for 'all'.
If I manually expand the variables to the following, then it suddenly starts to work! The console output from the logging is exactly the same, and I've been careful to avoid things like hidden characters.
all: ../api/common_api/CommonTypes.h ../api/common_api/CommonTypes.cpp
$(info The dependencies are $(IDL_HEADERS) $(IDL_CPPS))
Why is this makefile working with explicit dependencies, but not with variables?
UPDATE:
all: $(IDL_HEADERS) $(IDL_CPPS)
$(info The dependencies are $^)
$(info The dependencies should be $(IDL_HEADERS) $(IDL_CPPS))
outputs:
The dependencies are
The dependencies should be ../api/common_api/CommonTypes.h ../api/common_api/CommonTypes.cpp
make: Nothing to be done for 'all'.
This turned out to be an ordering problem. When the all rule is parsed, I hadn't set the IDL_INPUTS variable.
IDL_INPUTS gets set later, and the the all rule was run after that, showing the new updated values.
I am trying to compile bt from NPB. I am getting the attached errorCompilation Error . I have also attached the make file I am using.
What am I doing wrong in this case?
MakeFile:
SHELL=/bin/sh
BENCHMARK=bt
BENCHMARKU=BT
include ../config/make.def
OBJS = bt.o \
${COMMON}/c_print_results.o ${COMMON}/c_timers.o ${COMMON}/c_wtime.o
include ../sys/make.common
# npbparams.h is included by header.h
# The following rule should do the trick but many make programs (not gmake)
# will do the wrong thing and rebuild the world every time (because the
# mod time on header.h is not changed. One solution would be to
# touch header.h but this might cause confusion if someone has
# accidentally deleted it. Instead, make the dependency on npbparams.h
# explicit in all the lines below (even though dependence is indirect).
# header.h: npbparams.h
${PROGRAM}: config ${OBJS}
${CLINK} ${CLINKFLAGS} -o ${PROGRAM} ${OBJS} ${C_LIB}
.c.o:
${CCOMPILE} $<
bt.o: bt.c header.h npbparams.h
clean:
- rm -f *.o *~ mputil*
- rm -f npbparams.h core
Seems missing ../sys/setparams
Which should be an executable file, and takes bt A as input arguments.
It might be a depended tool should be built at first. I've tried a search on github, and could find some projects containing, ../sys/setparams.c, maybe, these are what you need.
Hope it helps you.
In Eclipse platform (Windows 10, MinGW toolchain), I'm trying to create a makefile to compile a project with .cpp and .hpp files.
To do that, I choose to create a new project:
File ->
(popup) New Project
C/C++ -> C/C++ Project => NEXT -> C++ Managed Build => MakefileProject -> Hello World C++ MakefileProject
This example compiles and links perfectly.
But I want to move the .cpp file into a src directory, then in the Project Explorer window, over the name of the project, I select to create a "Source
Folder", naming it as "src". Then I move the .cpp file inside the directory, and try to build the project without success.
How must I modify the makefile included with this example? I've tried everything but without luck. I get this error:
*19:51:33 **** Incremental Build of configuration Default for project CE_SEP ****
make all
make: *** No rule to make target CE_SEP.o', needed byCE_SEP.exe'. Stop*
Thanks for your support in advance!
Stop depending on an IDE. There is an actual "Makefile" that you can go in and edit. You likely just have to modify the path to the source file in the Makefile and/or add another Makefile in the "src" folder.
If you don't know Makefile syntax, google a brief tutorial.
Or save yourself some time in the long run and just learn CMake which is just a scripting type language to write platform-portable build systems -- it will generate Makefiles, MSVC projects, Xcode projects, Ninja build files, etc.
I have solved it. I had written wrongly the name of the file, and I have modified the Makefile adding "src\" before the name of the object an exe file:
CXXFLAGS = -O2 -g -Wall -fmessage-length=0
OBJS = src\CE.o
LIBS =
TARGET = src\CE.exe
$(TARGET): $(OBJS)
$(CXX) -o $(TARGET) $(OBJS) $(LIBS)
all: $(TARGET)
clean:
rm -f $(OBJS) $(TARGET)
But I rather will learn some of CMake as "jonrobm" suggested me.
Thank you again!
I am trying to compile my project which has the following structure
Project:
MakeFile
Executable
Source1
.cxx
.h
Source2
.cxx
.h
Build
*.o
And I'm having difficulty writting a Makefile to compile. I currently have commands like:
Src1 = $(wildcard $(SRCDIR1)/*.cxx)
Obj1 = $(patsubst $(SRCDIR1)/%.cxx, $(OBJDIR)/%.o, $(Src1))
But then I have difficulty making the compile rules for the object files a) Because I can no longer do:
$(Obj1): %.cxx
$(CXX) $(CFLAGS) -c $(#:.o=.cxx) -o $#
Because the '$#' command now includes the path of the build directory and b) because the prerequisites now include the build path and I should have a source path. I have read large bits of the make manual to try and find a solution but no luck.
Any help towards a solution appreciated!
Jack
From personal experience, after playing around a bit with "raw" Makefiles, I'd really recommend using some tool building the Makefiles for you, like automake or cmake.
You'll still have to specify all the source files manually - but at least I prefer that to manually fiddling around with the Makefiles.
One option I prefer is building an isomorphic directory structure in the build directory. That is, a source file ${src_dir}/project_x/main.cxx builds into ${build_dir}/project_x/main.o. This way you are protected from name clashes when there are source files with the same name in different source directories. The compiler rule would look something like:
${obj_dir}/%.o : ${src_dir}/%.cxx # % includes directory name, e.g. project_x/main
#-mkdir -p ${#D}
${CXX} -c -o $# ${CPPFLAGS} ${CXXFLAGS} $<
Notice how in the above it creates the target directory on the fly. This is a bit simplistic, in a real-world build system object files depend (using order-only dependency) on its directory, so that make automatically creates the destination directory if it does not exist instead of speculatively trying to create them for each target object file even if it already exists.
suppose we have a file-list:
src
a
b
c
Makefile
and there are many .cc & .h files in each folders.
how to write the Makefile??
when I write a path like this
./a/a.cc or ../a/a.cc
errors will be occurred.
but when i put the files on the same directory
and write as a.cc.
everything is ok.
I run it on cygwin.
could anyone help me?
The wildcard function is what you are looking for: http://www.gnu.org/software/make/manual/html_node/Wildcards.html
On Linux I would prefer Automake/Autoconf build systems: http://de.wikipedia.org/wiki/GNU_Build_System
An alternative could be CMake: http://www.cmake.org/
From the not-so-clear directory graph, it seems that you are missing the src/ directory prefix in your Makefile. E.g. to compile src/a/a.cc, use:
src/a/a.o: src/a/a.cc
$(CXX) $(CXXFLAGS) -c -o $# $<
BUT: Do yourself a favour, and use a real build system, such as CMake. It is cross-platform, can generate IDE project files (e.g. for Visual Studio, Xcode, Eclipse, CodeBlocks, etc.), is much higher level and does automatic dependency tracking for you.
You've left out a lot of details (e.g. where you want to put the object files), but VPATH is probably what you're looking for.
VPATH = src/a src/b src/c
# Now you can write rules as if the .cc & .h files were in the current directory.
%.o: %.cc
do something with $<
foo.o: foo.cc bar.h
do something special with $<