I'm getting the error "No targets specified and no makefile found. Stop."
however I'm running the "make" command for my Makefile.cpp in the same directory.
So I just wanted to do a simple makefile to run my three separate files:
all:
g++ gameoflife.cpp functions.cpp header.hpp -o gameoflife
The second line is tabbed once.
Let me know if I need to rename the files or how exactly to run the make file correctly. Thanks. Also this is all being run in a UNIX server with make installed, etc.
The make command uses the makefile with the the name that you specify with the -f option. If you don't use the -f options it uses the file Makefile without the .cpp appendix.
Your editor might have save your Makefile as Makefile.cpp. Check that you use the correct name.
Edit:
To be more specific: The GNU make searches for one of these files in that order:
GNUmakefile
makefile
Makefile
Related
I'm developing a C++ project which is going to be enclosed on a bigger one.
I've seen that on the bigger project (is a Qt application and it's being generated from qmake) I am able to compile a single file from the linux command line, just entering the relative path to the specific file as an argument to make.
On the other hand, I'm using CMake for my own project. When I modify some code for a compilation unit and I have to modify its header file, I have to wait a long time to compile its dependencies and then its own source file. But there are some situations in which I would prefer to check whether the source code in the *.cc file is compilable without errors.
Is there a way to generate a Makefile from CMake the way qmake does this? Switching to qmake is not an option anymore.
You do not have to add extra custom targets to your CMake scripts, as the Makefiles generated by CMake already contain .o targets for each .cc file. E.g. if you have a source file called mySourceFile.cc, there will be a Makefile in your build directory that defines a target called <Some Path>/mySourceFile.cc.o. If you cd into your build directory, you can use grep or ack-grep to locate the Makefile that defines this target, then cd into that Makefile's directory and build it.
E.g. suppose the command ack-grep mySourceFile.cc.o prints something like:
foo/bar/Makefile
119:x/y/z/mySourceFile.o: x/y/z/mySourceFile.cc.o
123:x/y/z/mySourceFile.cc.o:
124: # recipe for building target
Then you can build mySourceFile.cc.o by doing:
cd foo/bar && make x/y/z/mySourceFile.cc.o
CMake doesn't have a generic built-in way of doing this (it's an open issue), but if you're using the Ninja generator, you can can use a special Ninja syntax for building just the direct outputs of a given source file. For example, to compile just foo.o you would use:
ninja /path/to/foo.cpp^
Not out-of-the box. CMake does not expose those "internal" makefile rules in the main makefile.
You can do this only if you consider what kind of file structure CMake uses internally. You can e.g. for compiling a single .obj files using CMake generated makefiles call
make -f CMakeFiles/myProg.dir/build.make CMakeFiles/myProg.dir/main.cc.obj
when you have something like
cmake_minimum_required(VERSION 3.1)
project(myProg CXX)
file(WRITE "main.cc" "int main()\n{\nreturn 0;\n}")
add_executable(myProg main.cc)
To build src/foo.cpp alone:
cmake --build . --target src/foo.cpp.o
No, CMake does not offer built-in support to compile single files.
You have to add a target for each object file, maybe by a function iterating over all files of a directory.
Others have suggested ways to find the target name (ending in .cpp.o) from the .cpp filename, but if you already know the name of a target that will trigger compilation of the .cpp file and you're using ninja this suggestion should be easier.
First build the target:
ninja TriggersCppCompilationLib
Assuming your file was changed or was not yet built, ninja will print the full target name. When you see the name come up, hit enter so it is not overwritten. Then simply copy the name from the terminal (e.g. using tmux copy mode).
I'm not used to making makefiles. My old project had all the makefiles in place and I'm making this from scratch for a small test with a lot of canned lib dependencies that I'm not used to either. It's been a few years since I looked at makefiles.
I have a directory called libopcTest with the following in it:
LibOPCTest.cc
LibOPCTest.h
makefile
makefile has this in it:
INC=-I/usr/include/libxml2/libxml
LIB=-L/usr/include/libxml2/libxml
all: LibOPCTest.exe
LibOPCTest.exe: LibOPCTest.o
>tab> gcc -o LibOPCTest.exe LibOPCTest.o
LibOPCTest.o: LibOPCTest.cpp
>tab> gcc -c $(INC) $(LIB) LibOPCTest.cpp
clean:
>tab> rm LibOPCTest.o LibOPCTest.exe
I looked in /usr/include/libxml2/libxml and it does have xmlstring.h in it. I don't see the libxml reference in opc.h, but apparently that's where it comes in, presumably in an include file, like config.h.
Plus, we have LibOPCTest.cpp which #includes <opc/opc.h> and it's own .h file.
main is in LibOPCTest.cpp.
When I type make at the Linux command prompt, I get the following error:
In file included from /usr/include/opc/opc.h:36:0, from LibOPCTest.cpp:1:
/usr/include/opc/config.h:37:30: fatal error: libxml/xmlstring.h: no such file or directory.
Shouldn't I have the libxml with the LIB and INC definition in the makefile pointing to libxml? I don't think I'm supposed to add anything to opc.h, including build it, since it's a canned library.
I was looking at this makefile example, and I think I have everything I need (probably not since it's not building).
I know it's a basic question, but hopefully someone has a good suggestion. Thanks for being nice in advance!!
We decided to put the Linux version of libOPC on hold because there isn't a good 64 bit version and it needs a lot of work.
I am trying to compile a c++ file.
How do you configure gVIM to make/compile files using mingw32-make.exe
I get a shell returned 2 error and No targets specified and no makefile found
another thing i have noticed is that it's passing a C:\..\LOCALS~1\TEMP\something.tmp 2>&1 folder to mingw32-make.exe
On the vim command line:
:set makeprg=c:/path/to/mingw32-make.exe
Once you have it working, put the set command in .vimrc
Edit:
Is there a file named Makefile in the current directory?
If not, create Makefile in the current directory and have it call your makefile.
For example, if you build your software with mingw32-make project.mak create Makefile with contents something like this:
all:
mingw32-make project.mak
I have a problem because i have never written any makefile. So if any could help me I become happy. I have a lot of different .o files, which stored in the different folders. For example:
folder1: obj1.o
folder2: obj2.o
folder3: obj3.o
I need makefile, which will build the library from files which I send to makefile like param. Param should be makefile too and include info about folders where stored necessary files.
For example I would like to build lib from objects stored at folder1 and folder2 without folder3. So makefile which I send as param to the main makefile must include routes to folder1 and folder2:
local_libs := ../folder1
local_libs += ../folder2
main makefile should parse that info and call libtool utilite for creating lib from files at this folders. Could anybody help?
I suppose it is easy for realization, example will be great!
You need a rule that inputs the .o files, outputs the .a file and calls the ar command to do the work. Something like:
lib.a: $(OBJECTS)
${AR} -cr ${#} ${^}
GNU make does not support passing parameters "to the makefile" on the command line.
You have two basic mechanism for setting parameters to be used by make while executing a makefile (I'm assuming that you are using GNU make, and not all of his advice will apply to other makes):
Write to submakefiles, possibly using a script. If you makefile has a line like
include file.mk
gmake will include the contents of file.mk. Change the contents of file.mk and you change the behavior of your makefile.
Make can take variable values from environment variables when set. This provides a powerful mechanism for letting the user customize the behavior of your makefile.
I'm a newbie and I've a problem!
I've to work with a c++ code and I don't know how to import it and how to compile it on eclips ( I compiled it by command line).
The code has a particular structure and it is organized in this way:
repos____lib____configure (execute the configure file inside the libraries folders)
I I___makefile (execute the make file inside the libraries folders,
requires make/make.def)
I I___ib1____.cpp
I I I____.h
I ... I____configure (it requires make/configure_lib and
make/configure_includes
I ... I____makefile (generated by configure)
I I___lib2___....
i I___.......
I I___libn____.cpp
i I____.h
i I____configure
i I____makefile (generated by configure)
I
I___make(folder)__bashrc (are set the some environment variables)
I I__configure_bin
I I__configure_includes
I I__configure_lib
I I__make.def (are set all the include path and library path used
I in the configure file)
I___application__main.cpp
I__configure
I__makefile(generated by the configure file)
to be sure that you understand my problem...(sure... :) )
the first configure file is:
cd lib1; ./configure
cd ../lib2; ./configure
.....
....
cd ../libn; ./configure
cd
and the first makefile is
include /media/Dati/WORKHOME/repos/make/make.def
this is the makefile for the whole library
lib:
make -C lib1
make -C lib2
make -C libn
an example of configure file (the one inside lib1):
#!/usr/bin/perl
$INC = '$(OPENCVINC) $(FLTKINC) $(DC1394V2INC)'; ##<-DEFINED IN /make.def
$LIB = '$(OPENCVLIB) $(FLTKLIB) $(DC1394V2LIB)'; #####################
#-------------------------------------------------------------------------------
require '/media/Dati/WORKHOME/repos/make/configure_lib';
print "Created Makefile.\n";
# this will create a include file for the whole directory,
# using the template <dirname>.h.templ
require '/media/Dati/WORKHOME/repos/make/configure_includes';
print "Created $libname.h\n";
compile it without eclipse is simple
type /.configure in the lib folder
type make
go into the application folder
type ./configure
type make
run the program
my question is....in eclipse???
I imported the three with import/ import existing code as makefile project but now I don't know how compile it.
could you please help me? it's important!
thank you very much
gabriele
You have done the right thing by using "import existing code as makefile project".
Now eclipse know that it needs to call make and use your makefile. But Your build process is not only driven by make.
One solution is to write a makefile that call all your build steps. Something Like :
all:
cd dir1 && ./configure && make
cd dir2 && ./configure && make
etc.
my2c
Edit:
I currently have no eclipse installed, so I can not send you detailled steps ... sorry