I'm having issues getting my Makefile to work for a simple C++ project.
The error I am getting is
"fatal-error: no input files"
Here is my project structure:
ROOT
|
|___Makefile
|
|___bin
|
|___src
| |
| |___main.cpp
|
|___include
|
|___GL
| |
| |___glew.h
| |___glfw3.h
|
|___glm
|
|___glm.hpp
And Here is my Makefile:
CC = g++
INC_DIR1 = include/GL
INC_DIR2 = include/glm
SRC_DIR = src
OBJ_DIR = bin
CFLAGS = -c -Wall -I
SRCS = $(SRC_DIR)/main.cpp
OBJS = $(OBJ_DIR)/main.o
DEPS = $(INC_DIR1)/glew.h $(INC_DIR1)/glfw3.h $(INC_DIR2)/glm.hpp
EXECUTABLE = game
all: $(OBJS) $(EXECUTABLE)
$(OBJ_DIR)/%.o : $(SRC_DIR)/%.cpp
$(CC) $(CFLAGS) $< -o $#
$(EXECUTABLE): $(OBJS)
$(CC) $(OBJS) -o $#
$(OBJ_DIR)/main.o: $(DEPS)
I'm not sure if its trying to find .ccp files for the header files or If I set my Makefile up incorrectly. I'm pretty new to Makefiles so any insight would be much appreciated.
Thanks.
EDIT:
So I was able to resolve most of the issues I was having however now I am getting the following error when I try to make my program via command line:
:multiple definition of `main'
c:/mingw/bin/../lib/gcc/mingw32/4.8.1/../../..\libmingw32.a(main.o):main.c:(.tex
t.startup+0x0): first defined here
c:/mingw/bin/../lib/gcc/mingw32/4.8.1/../../..\libmingw32.a(main.o):main.c:(.tex
t.startup+0xa7): undefined reference to `WinMain#16'
c:/mingw/bin/../lib/gcc/mingw32/4.8.1/../../../../mingw32/bin/ld.exe: c:/mingw/b
in/../lib/gcc/mingw32/4.8.1/../../..\libmingw32.a(main.o): bad reloc address 0x2
0 in section `.eh_frame'
collect2.exe: error: ld returned 1 exit status
make: *** [game.exe] Error 1
Below is my Updated Makefile
#Makefile
CC = g++
INC_DIR = include
LIB_DIR = lib
SRC_DIR = src
OBJ_DIR = bin
CFLAGS = -Wall -I $(INC_DIR)
LDFLAGS = -L $(LIB_DIR) -static -lglfw3 -lmingw32
OPTIONS = -std=c++0x -O3
SRCS = $(SRC_DIR)/main.cpp
OBJS = $(OBJ_DIR)/main.o
EXECUTABLE = game.exe
all: $(EXECUTABLE)
$(EXECUTABLE) : $(SRCS)
$(CC) $(CFLAGS) $(LDFLAGS) $< -o $#
clean:
rm $(EXECUTABLE)
I know the issue is that it is finding two main methods in a file somewhere in my mingw32 library but I am unsure as to how I should go about resolving the error.
Please show the command that was invoked and the exact error you got, cut and pasted. It would have taken me about 1/20th the time to see what was wrong if you'd have done that.
Here's your problem:
CFLAGS = -c -Wall -I
$(OBJ_DIR)/%.o : $(SRC_DIR)/%.cpp
$(CC) $(CFLAGS) $< -o $#
Expanded out, this will run the following command:
g++ -c -Wall -I src/main.cpp -o bin/main.o
The problem here is you've got -I in your CFLAGS, with no directory after it. That means that the next word, in this case src/main.cpp, is taken to be the directory to be added to the include line.
Probably you want something like:
CFLAGS = -c -Wall -I$(INC_DIR1) -I$(INC_DIR2)
Related
I've looked at several similar posts reporting this error however, the majority seem to be related to running make in a different folder than that of the source files. In my case, the cpp files are in the same folder as my makefile from which I am running the make command. It seems my rule cannot locate 'AudioHandler.cpp' despite it being in the same folder as the makefile itself. I assume there is an error with a path somewhere, as this file is suspiciously the first one in the list! What am I doing wrong?
# compiler to use
CXX = g++
# header folder
IDIR = ../include
# compile flags
CXXFLAGS = -I$(IDIR) -Wall -std=c++0x `sdl2-config --cflags` `sdl2-config --libs` -lSDL_mixer
# output folder
ODIR = obj
# build folder
BDIR = ../build
# engine dependencies
_DEPS = AudioHandler.hpp Callback.hpp Entity.hpp Font.hpp Game.h GameMap.hpp GameMath.h InputHandler.hpp MapHandler.hpp Matrix3x3.hpp Matrix4x4.hpp Palette.hpp ScreenHandler.hpp Structs.h System.hpp Ticker.hpp Utilities.hpp Vec2.hpp Vec3d.hpp ZX_Palette.hpp Scene.h UpdateComponent.hpp vec2.hpp
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
# engine cpp directory
_OBJ = AudioHandler.o Callback.o Entity.o Font.o Game.o GameMap.o InputHandler.o MapHandler.o Matrix4x4.o Palette.o ScreenHandler.o System.o Ticker.o Utilities.o Vec2.o Vec3d.o ZX_Palette.o vec2.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
$(ODIR)/%.o: %.cpp $(DEPS)
$(CXX) -c -o $# $< $(CXXFLAGS)
$(BDIR)/libgameengine.a: $(OBJ)
ar rcs $# $^
I have this makefile:
IDIR = include
SDIR = src
ODIR = obj
BDIR = build
DEPS = $(shell find $(IDIR)/ -name '*.hpp')
SRCS = $(shell find $(SDIR)/ -name '*.cpp')
OBJS = $(patsubst %.cpp,$(ODIR)/%.o,$(notdir $(SRCS)))
BIN = main
CPPC = g++
CFLAGS = -Wall -c
all: dir $(BDIR)/$(BIN)
#echo Finished compiling $(BIN)
dir:
mkdir -p $(BDIR)
mkdir -p $(ODIR)
$(BDIR)/$(BIN): $(OBJS)
$(CPPC) $^ -o $#
$(OBJS): $(SRCS)
$(CPPC) $(CFLAGS) $^ -o $#
clean:
rm -rf $(BDIR) $(ODIR)
When I try to make, I get the following error:
mkdir -p build
mkdir -p obj
g++ -Wall -c src/sdk/tcp/Tcp.cpp src/sdk/socket/Socket.cpp src/Main.cpp -o obj/Tcp.o
g++: fatal error: cannot specify ‘-o’ with ‘-c’, ‘-S’ or ‘-E’ with multiple files
compilation terminated.
make: *** [Makefile:27: obj/Tcp.o] Error 1
My question is, is it possible to achieve what I am trying with this makefile? Going through each source file in $(SRCS), and compile the object file directly inside the obj directory with just the basename. An example of obj directory after a successful compilation:
obj
/ | \
/ | \
Tcp.o Socket.o Main.o
Your $(OBJS) rule is wrong.
There are (at least) two ways to do this.
You could write a pattern rule and use vpath to locate the sources:
vpath %.cpp $(dir $(SRCS))
$(OBJS): obj/%.o: %.cpp
$(CPPC) $(CFLAGS) $^ -o $#
Or you could generate a rule for each object:
define template
$(patsubst %,obj/%.o,$(notdir $(1))): $(addsuffix .cpp,$(1))
echo $(CPPC) $(CFLAGS) $$^ -o $$#
endef
$(foreach src,$(SRCS),$(eval $(call template,$(basename $(src)))))
In expansion to my previous question how to write a makefile for structured file system:
The file structure:
.
├── Headers
│ ├── function.h
│ └── test.h
├── makefile
├── README.md
└── Sources
├── function.c
├── main.c
└── test.c
I'm trying to write a makefile that reads the #include<...> on any given source file and compile as required.
Originally I used to have a make file that looked like this:
INC_DIR = Headers
SRC_DIR = Sources
OBJ_DIR = Objects
#CXXFLAGS = -c -Wall -I. -IHeaders
CXXFLAGS = -c -Wall -I. -IHeaders
CC = gcc
SRCS = $(SRC_DIR)/*.c
OBJS = $(OBJ_DIR)/*.o
#The wildcard and patsubt commads will come handy
DEPS = $(INC_DIR)/*.h
#need to use an automatic dependency generator
output: $(OBJ_DIR)/main.o $(OBJ_DIR)/function.o
$(CC) $^ -o $#
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c $(DEPS)
$(CC) $(CXXFLAGS) $< -o $#
run: output
./output
clean:
rm $(OBJ_DIR)/*.o
rm output
-#echo "Clean completed"
That meant that for every source file that output was dependent on i had to add that object to this line.
output: $(OBJ_DIR)/main.o $(OBJ_DIR)/function.o $(OBJ_DIR)/test.o
$(CC) $^ -o $#
And is any other source file was dependent on one or more sources additional rules had to be added.
To solve this:
here is what I have gathered from Auto-Dependency Generation and 4.14 Generating Prerequisites Automatically
As mentioned by the community members, I have a mixed understanding of dependency generation and how to make use of the files generated.
DEP_DIR = .d
$(shell mkdir -p $(DEP_DIR) >/dev/null)
DEPFLAGS = -MT $# -MMD -MP -MF $(DEP_DIR)/$*.Td
INC_DIR = Headers
SRC_DIR = Sources
OBJ_DIR = Objects
$(shell mkdir -p $(OBJ_DIR) >/dev/null)
CXXFLAGS = -c -Wall -I. -IHeaders
CC = gcc
SRCS = $(SRC_DIR)/*.c
OBJS = $(OBJ_DIR)/*.o
#The wildcard and patsubt commads will come handy
#DEPS = $(INC_DIR)/*.h
MAKEDEPEND = $(CC) $(CXXFLAGS) $< \
| sed -n 's/^\# *[0-9][0-9]* *"\([^"]*\)".*/$*.o: \1/p' \
| sort | uniq > $*.Td
COMPILE.c = $(CC) $(DEPFLAGS) $(CXXFLAGS)
#need to use an automatic dependency generator
#%.d: %.c
# #set -e; rm -f $#; \
# $(CC) -MP -MD $(CXXFLAGS) $< > $#.$$$$; \
# sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
# rm -f $#.$$$$
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c $(DEP_DIR)/%.d
#$(MAKEDEPEND); \
cp $*.Td $*.d; \
sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
-e '/^$$/ d' -e 's/$$/ :/' < $*.Td >> $*.d; \
rm -f $*.Td
#$(COMPILE.c) -o $# $<
$(CC) $(CXXFLAGS) $(DEPFLAGS) $< -o $#
-include $(SRCS:.c=.d)
$(DEP_DIR)/%.d: ;
.PRECIOUS: $(DEP_DIR)/%.d
output: $(OBJS)
$(CC) $^ -o $#
run: output
./output
clean:
rm -r $(OBJ_DIR)
rm -r $(DEP_DIR)
rm output
-#echo "Clean completed"
The error when make is executed is:
$ make
gcc -c -Wall -I. -IHeaders -MT Objects/*.o -MMD -MP -MF .d/*.Td Sources/function.c -o Objects/*.o
gcc Objects/*.o -o output
/usr/lib/gcc/x86_64-linux-gnu/5/../../../x86_64-linux-gnu/crt1.o: In function `_start':
(.text+0x20): undefined reference to `main'
collect2: error: ld returned 1 exit status
makefile:48: recipe for target 'output' failed
make: *** [output] Error 1
So, I'm hoping to achieve the auto dependency detection and compilation. I think the error is in the way that the dependencies are detected and the way they are generated for a given source file.
It looks to me like you're trying to combine multiple different ways of generating dependency info, and that can't work. The advanced post talks about multiple ways to solve the problem: you need to pick one not try to use them all together.
If you want to use the advanced method then use it as described in the "TL;DR" section at the top, or else in the "Combining Compilation and Dependency Generation" section at the bottom. If you're using GCC there's no need for MAKEDEPEND, sed, etc.
The advanced post says that your rule should look like this:
COMPILE.c = $(CC) $(DEPFLAGS) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
POSTCOMPILE = mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d
%.o : %.c
%.o : %.c $(DEPDIR)/%.d
$(COMPILE.c) $(OUTPUT_OPTION) $<
$(POSTCOMPILE)
That's it.
Previously I was struggling with creating a makefile in root directory that would deal with source files being in src folder and headers in include folder. Following this I wanted to add another folder tests where I would keep .cpp files with tests. Unfortunately I have problems with this.
The folder structure is:
.
|__makefile
|
|__/src
| |
| |__[regular .cpp files]
|
|__/include
| |
| |__[.h files]
| |
| |__/gtest
| |
| |__gtest.h
|
|__/tests
|
|__test_factorial.cpp
./tests/test_factorial.cpp:
#include "gtest/gtest.h"
#include "factorial.h"
// some tests
makefile:
CC = g++
CFLAGS = -Wall
INCLUDES = -I./include
LIBS = -lgtest -lpthread
SOURCEDIR = ./src/
SRCS = $(shell find ./src/ -name '*.cpp')
SRCS += $(shell find ./tests/ -name '*.cpp')
.PHONY: clean depend
SRCS := $(filter-out ./tests/main_tests.cpp, $(SRCS))
OBJS = $(SRCS:.cpp=.o)
OBJS := $(OBJS:./src%=.%)
release: $(OBJS)
$(CC) $(CFLAGS) -o app $(OBJS) $(LIBS)
VPATH = ./src:./tests
%.o: ./src/%.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c ./src/$*.cpp
%.o: ./tests/%.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c ./tests/$*.cpp
depend: .depend
.depend: $(SRCS)
rm -f ./.depend
$(CC) $(CFLAGS) $(INCLUDES) -MM $^ > ./.depend;
include .depend
When I execute make from the root directory all the files from /src compile fine (I end up having object files in the root directory for them) but I get an error for .cpp file from /tests directory:
g++ -c -o tests/test_factorial.o tests/test_factorial.cpp
tests/test_factorial.cpp:1:25: fatal error: gtest/gtest.h: No such file or directory
compilation terminated.
<builtin>: recipe for target 'tests/test_factorial.o' failed
make: *** [tests/test_factorial.o] Error 1
What might be important, the .depend file seems to have it all right:
test_factorial.o: tests/test_factorial.cpp include/gtest/gtest.h \
include/factorial.h
What is wrong with the makefile?
EDIT
I believe this fragment of the error:
<builtin>: recipe for target 'tests/test_factorial.o' failed
suggests that something is wrong in this part of the makefile:
%.o: ./src/%.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c ./src/$*.cpp
%.o: ./tests/%.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c ./tests/$*.cpp
Why it's trying to do ./tests/test_factorial.o rather than ./test_factorial.o? Let me underline again that object files for ./src/*.cpp files end up in root directory, i.e. ./*.o, not ./src/*.o.
Your makefile is building
tests/test_factorial.o
from
tests/test_factorial.cpp
and that doesn't match the rule
%.o: ./tests/%.cpp
So it is instead using a builtin rule. (As an aside, the convention is to build c++ files using $(CXX) and $(CXXFLAGS) not $(CC)).
Try a rule pattern of
./tests/%.o: ./tests/%.cpp
The reason that your Makefile uses the name tests/test_factorial.o is because
OBJS = $(SRCS:.cpp=.o)
which (it should be obvious) makes the path to the .o file the same as the path to the .cpp.
You have a subsequent rule stripping the path src/
OBJS := $(OBJS:./src%=.%)
and no similar rule for tests/
I have the following directory structure
(root)
/ / \ \
/ | | \
src obj include bin
I would like to use an implicit rule to compile all the .cc files in root\src to .o files in root\obj.
This is my makefile so far:
basedir = .
incl = ${basedir}\include
obj = ${basedir}\obj
src = ${basedir}\src
lib = ${basedir}\lib
bin = ${basedir}\bin
CXX = gcc
LDLIBS = -lstdc++ -lmingw32 -lSDLmain -lSDL -lSDL_image -lchipmunk -lSDL_ttf \
-lSDL_mixer
LDFLAGS = -L${lib}
objects = $(addprefix ${obj}\, GameObject.o PhysicalObject.o \
Terrain.o Timer.o main.o ImageLoader.o Player.o )
sources = $(addprefix ${src}\, GameObject.cc PhysicalObject.cc \
Terrain.cc Timer.cc main.cc ImageLoader.cc Player.cc )
Cyborg : ${objects}
${CXX} ${objects} -o ${bin}\Cyborg.exe -L${lib} ${LDFLAGS} ${LDFLAGS}
${obj}\%.o : ${src}\%.c
${CXX} ${src}\$^ -c -o ${obj}\$#
.PHONY: clean
clean :
rm ${bin}\Cyborg.exe ${objects}
The error that I get is make: *** No rule to make target .\obj\GameObject.o, needed by Cyborg. Stop.
Any idea what's going wrong? I'm pretty new to makefiles so this might be terribly obvious.
Applying all of the ideas from the comments (and adding a couple trivial ones of my own), we get:
basedir = .
incl = ${basedir}/include
obj = ${basedir}/obj
src = ${basedir}/src
lib = ${basedir}/lib
bin = ${basedir}/bin
CXX = g++
LDLIBS = -lstdc++ -lmingw32 -lSDLmain -lSDL -lSDL_image -lchipmunk -lSDL_ttf \
-lSDL_mixer
LDFLAGS = -L${lib}
objects = $(addprefix ${obj}/, GameObject.o PhysicalObject.o \
Terrain.o Timer.o main.o ImageLoader.o Player.o )
sources = $(addprefix ${src}/, GameObject.cc PhysicalObject.cc \
Terrain.cc Timer.cc main.cc ImageLoader.cc Player.cc )
Cyborg : ${objects}
${CXX} ${objects} -o ${bin}/Cyborg.exe -L${lib} ${LDFLAGS} ${LDFLAGS}
${obj}/%.o : ${src}/%.c
${CXX} $^ -c -o $#
.PHONY: clean Cyborg
clean :
rm -f ${bin}\Cyborg.exe ${objects}
What does "make Cyborg" do with this Makefile?
This is probably going to take a few iterations.
Try some simple rules, in order of increasing complexity, and tell us the results:
./obj/GameObject.o : ./src/GameObject.cc
#echo trying to build $# from $<
./obj/GameObject.o : ./obj/%.o : ./src/%.cc
#echo trying to build $# from $<
$(objects) : ./obj/%.o : ./src/%.cc
#echo trying to build $# from $<
./obj/%.o : ./src/%.cc
#echo trying to build $# from $<
${obj}\%.o : ${src}\%.c --> ${obj}\%.o : ${src}\%.cc
I had similar problem with GNU make. Try making explisit rules for your objects:
$(obj)\GameObject.o: $(src)\GameObject.cc
$(obj)\PhysicalObject.o: $(src)\PhysicalObject.cc
# and so on for each object