I have a "parent" Makefile, and I am executing other Makefiles from it using make -C.
I am currently passing variables from the parent to its children by appending the variables to the make commands. This makes for quite a cumbersome pattern, for example:
$(MAKE) -C $# PREFIX="$(PREFIX)" CXXFLAGS="$(CXXFLAGS)" FOO="$(FOO)"
This makes for a lot of repetition, especially if there is a long list of $(MAKE) calls passing similar variables.
Is there a more elegant / optimal way to pass variables to a child invocation of make?
You can export them through the environment:
export PREFIX CXXFLAGS FOO
However, note that if these variables are actually set in the child makefile then this will not override those settings.
Related
# makefile
SHELL:=/bin/bash
PATH:=/path/to/new/programs:$(PATH)
my_var:=$(shell which program)
rule:
echo $(my_var)
which program
#output
$: make rule
echo
which program
/path/to/program
# prints nothing
I have tried everything, and actually recall getting this to work as I was creating the makefile earlier. It is turning into a quagmire--all I need to do is check whether an exe exists before I install it.
Does the explicit which work if you don't set the SHELL variable in your makefile?
Setting the SHELL variable only impacts recipes. It's not used for the $(shell ...) function. You can use:
my_var := $(shell /bin/bash -c 'which function')
However on my system even using the default shell works with which. Maybe your system is different somehow.
Note of course which finds programs, not functions...
RE-WRITTEN
(Thanks to #MadScientist for pointing out my confusion.
I thought it best to completely delete the erroneous info.)
As $PATH was originally exported into make's environment,
make will ensure that it is exported into the environment of any recipe commands that it runs.
Any change made to $PATH in the makefile will make its way through to the environment of receipe commands run by make.
Note that this is not true for commands run via $(shell …).
Exported variables keep the values they had when make started.
Any changes they suffer within the makefile are ignored as far as the external commands are concerned.
As pointed out elsewhere,
one workaround is to explicitly repeat the augmentation of $PATH in any $(shell …)
my_var := $(shell PATH='${PATH}' which program)
(Surprises me. Is this a make bug? Or at least a documentation bug?)
I have a bunch of qmake-generated makefiles each of which call make inside them (recursive make) in a chained manner.
After my build is over, the qmake-generated makefiles are all on disk so you'd think I could just call make on one of them if I wanted to 'replay' one particular makefile. Wrong.
When I try make-ing one, it fails, probably because there's a bunch of (environment) variables that it normally inherits from the calling makefile during the normal build.
Except for the variables, each qmake-generated makefile is pretty self-contained.
QUESTION
How can I simulate the 'normal' environment for a given recursive make so that I can call it in isolation?
I'm thinking I'd have to do something with the --print-data-base output: parse it and then call make with the same vars and values it had during the normal build.
WHY
I'm doing this because I need to modify the compile commands for ONE makefile but it's all controlled by the top-level .conf and I'm getting in way too deep.
I assume the problem is that you need to find this information before you get a chance to make any changes to the generated makefiles. Therefore, this solution is focused on shell commands (I'm assuming you're on Linux, since you don't say).
After starting your build, the first time, use something like:
ps -ef | head -1
ps -ef | grep make
to find make processes involved in the build. The PID column lists the Process ID of the make process, while the PPID column lists that of its parent. Use this information to find the top-level make process. Then, run:
strings /proc/<pid>/environ | sort > /tmp/make_env
env | sort > /tmp/normal_env
diff /tmp/normal_env /tmp/make_env
This will show you how the make process' environment differs from that of your current shell.
Now, that might not solve your problem, because GNU Make allows variables to be specified as commandline parameters. So, you should also check how it's being run:
strings /proc/<pid>/cmdline
That will print each commandline argument of <pid>, on a separate line.
BTW, when variables are passed to GNU Make via commandline arguments, they're handled by overriding any instance of the same variable, that might be contained within the makefile.
Within a makefile, you can see its environment using:
$(info My environment is $(shell env))
You can see its commandline options using:
$(info MAKEFLAGS = $(MAKEFLAGS))
If you only want to see the overrides, use MAKEOVERRIDES:
$(info MAKEOVERRIDES = $(MAKEOVERRIDES))
Finally, the targets can be seen using:
$(info MAKECMDGOALS = $(MAKECMDGOALS))
I have a makefile, ImpTarget.mk, defined with following content, taken from this example:
%.h: %.dummy_force
#echo header= $# xyz
%.dummy_force: ;
I include this file in the MAKEFILES variable
This is my top-level makefile (modified with the MAKEFILES variable)
MAKEFILES = "C:\Users\User1\Desktop\A\ImpTarget.mk"
all:
$(MAKE) -C src -f makefile_gen all
$(MAKE) -C src DEBUG=TRUE -f makefile_gen all
My goal is to turn all files - .h, .cpp, etc - in the prerequisites list into targets also i.e., executing make --print-database should yield a statement that every header file is also a target.
However, it's not working.
When I look at the database printed out, for each makefile I see that MAKEFILES is equal to "C:\Users\User1\Desktop\A\ImpTarget.mk" which is good because it means that it should be reading in ImpTarget.mk
3.4 The Variable MAKEFILES
If the environment variable MAKEFILES is defined, make considers its
value as a list of names (separated by whitespace) of additional
makefiles to be read before the others.
But it is not turning each file into a target. I still get:
# Not a target:
C:/Users/User1/Desktop/A/HMI_FORGF/qt5binaries/include/QtCore/qglobalstatic.h:
# Implicit rule search has been done.
# Last modified 2016-05-12 10:10:13
# File has been updated.
# Successfully updated.
In fact, the rule I defined is not even showing up in the --print-data-base part of the output.
I put the xyz as a marker so I could easily locate it in the listing of the rules that are executed but it doesn't appear in that list.
Why not use include?
Well first of all, what's the difference? Show me a link.
Secondly, yes that's the preferred method but some of my makefiles auto-generate a makefile, then inside that one generate another makefile and execute it.
So I don't have control over my build system enough to do that.
If the environment variable MAKEFILES is defined
Meaning make will only consider MAKEFILES if it is defined externally to make, either in the shell environment itself or by running make MAKEFILES=foo.mk.
MAKEFILES vs include is explained in the next paragraph
The main use of MAKEFILES is in communication between recursive invocations of make
You need to export the MAKEFILE variable into the environment. From 6.10 Variables from the Environment
When make runs a recipe, variables defined in the makefile are placed into the environment of each shell. This allows you to pass values to sub-make invocations (see Recursive Use of make). By default, only variables that came from the environment or the command line are passed to recursive invocations. You can use the export directive to pass other variables. See Communicating Variables to a Sub-make, for full details.
Since MAKEFILES wasn't found in the original environment, it isn't automatically passed into the environment. Use:
export MAKEFILES = "C:\Users\User1\Desktop\A\ImpTarget.mk"
I have one problem. I cannot set multiple variables depending on target. I need to set two variables for example if makefile has been run with option cpp (target), two variables should be set,but I get only one variable (CC) set. But another is left as default.
cpp:EXTENSION=cpp
cpp:CC=g++
cpp:COMPILE
Please help with this problem.
I cannot set multiple variables depending on target.
In GNU Make, this is typically achieved by analyzing the content of the $(MAKECMDGOALS) variable and then setting the variables depending on the specified goals.
For example, a Makefile:
ifeq ($(filter cpp,$(MAKECMDGOALS)),cpp)
MSG=make cpp was called!
endif
ifeq ($(filter notcpp,$(MAKECMDGOALS)),notcpp)
MSG=make notcpp was called!
endif
all:
#echo possible targets: cpp, notcpp; false
notcpp cpp:
#echo $(MSG)
Running the make cpp would print make cpp was called!.
Running the make notcpp would print make notcpp was called!.
(Explanation of the ifeq ($(filter cpp,$(MAKECMDGOALS)),cpp) construct. The $(filter) function looks for the word (first argument, cpp) in the list (second argument, $(MAKECMDGOALS)). If it finds the word, it returns it. Otherwise, it returns an empty string. The ifeq then compares the result of the $(filter) function to the sought word: if equal, then the block til endif is parsed/executed. Alternatively, one could write ifneq ($(filter cpp,$(MAKECMDGOALS)),) to test that the result of $(filter) is not an empty string. For more info, see $(filter) and ifeq in GNU Make documentation. Additionally, about general function syntax and how to call a custom function.)
Another possibility is using multiple Makefiles. In the main Makefile, depending on the target you pass the control to the target-specific Makefile, e.g.:
cpp notcpp:
$(MAKE) -f Makefile.$# all
Use of target-specific includes is also a popular option.
I'm using a tool chain where I do not know the names of all of the intermediate files.
E.g. I know that I start out with a foo.s, and go through several steps to get a foo.XXXX.sym and a foo.XXXX.hex, buried way down deep. And then running other tools on foo.XXXX.hex and foo.XXXX.sym, I eventually end up with something like final.results.
But, the trouble is that I don't know what the XXXX is. It is derived from some other parameters, but may be significantly transformed away from them.
Now, after running the tool/steps that generate foo.XXXX.{sym,hex}, I now typically scan the overall result directory looking for foo.*.{sym,hex}. I.e. I have code that can recognize the intermediate outputs, I just don't know exactly what the names will be.
I typically use make or scons - actually, I prefer scons, but my team highly prefers make. I'm open to other build tools.
What I want to do is be able to say (1) "make final.results", or "scons final.results", (2) and have it scan over the partial tree; (3) figure out that, while it does not know the full path, it definitely knows that it has to run the first step, (4) after that first step, look for and find the foo.XXX.* files; (5) and plug those into the dependency tree.
I.e. I want to finish building the dependency tree after the build has already started.
A friend got frustrated enough with scons' limitations in this area that he wrote his own build tool. Unfortunately it is proprietary.
I guess that I can create a first build graph, say in make with many .PHONY targets, and then after I get through the first step, generate a new makefile with the new names, and have the first make invoke the newly generated second makefile. Seems clumsy. Is there any more elegant way?
GNU make has an "auto-rexec" feature that you might be able to make use of. See How Makefiles Are Remade
After make finishes reading all the makefiles (both the ones found automatically and/or on the command line, as well as all included makefiles), it will try to rebuild all its makefiles (using the rules it knows about). If any of those makefiles are automatically rebuilt, then make will re-exec itself so it can re-read the newest versions of the makefiles/included files, and starts over (including re-trying to build all the makefiles).
It seems to me that you should be able to do something with this. You can write in your main makefile and "-include foo.sym.mk" for example, and then have a rule that builds "foo.sym.mk" by invoking the tool on foo.s, then running your "recognized the next step" code and generate a "foo.sym.mk" file which defines a rule for the intermediate output that got created. Something like (due to lack of specificity in your question I can't give true examples you understand):
SRCS = foo.s bar.s baz.s
-include $(patsubst %.s,%.sym.mk,$(SRCS))
%.sym.mk: %.s
<compile> '$<'
<recognize output and generate makefile> > '$#'
Now when make runs it will see that foo.sym.mk is out of date (if it is) using normal algorithms and it will rebuild foo.sym.mk, which as a "side effect" causes the foo.s file to be compiled.
And of course, the "foo.sym.mk" file can include ANOTHER file, which can recognize the next step, if necessary.
I'm not saying this will be trivial but it seems do-able based on your description.
Make constructs the graph before running any rule, so there won't be a perfect answer. Here are some reasonably clean solutions.
1) use PHONY intermediates and wildcards in the commands. (You can't use Make wildcards because make expands them before running rules.)
final.results: middle
# build $# using $(shell ls foo.*.sym) and $(shell ls foo.*.hex)
.PHONY: middle
middle: foo.s
# build foo.XXXX.sym and foo.XXXX.hex from $<
2) Use recursive Make (which is not as bad as people say, and sometimes very useful.)
SYM = $(wildcard foo.*.sym)
HEX = $(wildcard foo.*.hex)
# Note that this is is the one you should "Make".
# I've put it first so it'll be the default.
.PHONY: first-step
first-step: foo.s
# build foo.XXXX.sym and foo.XXXX.hex from $<
#$(MAKE) -s final.results
final.results:
# build $# using $(SYM) and $(HEX)
3) Similar to 2, but have a rule for the makefile which will cause Make to run a second time.
SYM = $(wildcard foo.*.sym)
HEX = $(wildcard foo.*.hex)
final.results:
# build $# using $(SYM) and $(HEX)
Makefile: foo.s
# build foo.XXXX.sym and foo.XXXX.hex from $<
#touch $#