I would appreciate if anyone could help me with the Makefile error. I would like to compile a C++ application into a shared library and place the compiled object *.o files in ./sobjs directory like below. I followed several examples to do this, however I still have the problem to get this correct compilation and linker.
Makefile:
OBJS = a1.o a2.o a3.o a4.o a5.o
objects = sobj/$(OBJS)
all: $(objects)
$(CXX) $(CXX_FLAGS) $(objects) -shared -o libname.so
$(objects) : | sobjs
sobjs:
#mkdir -p $#
sobjs/%.o: %.cpp
#echo $<
$(CXX) -fPIC -c -o $# $< $(CXX_FLAGS) $(MY_FLAGS) $(INCLUDE_DIRS)
I made a mistake. Replace this
objects = sobj/$(OBJS)
with this
objects = $(patsubst %.o, sobjs/%.o,$(OBJS))
and it will now compile files correctly.
Related
I am trying to create a makefile for my project, but i seem to run into some errors, as I am testing new things. My file structure is as such:
~/main #root project folder
~/main/include #header files (mostly class headers)
~/main/src #source files
~/main/src/obj #object files
Makefile
(Makefile is in the root project folder)
Makefile:
CC=g++
IDIR=include
SDIR=src
ODIR=src/obj
DEPS=$(IDIR)/%.h
OBJS=$(ODIR)/%.o
SRCS=$(SDIR)/%.cpp
CFLAGS=-Wall -std=c++11 -I$(IDIR)
$(OBJS): $(SRCS) $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
all: $(OBJS)
gcc -o run $^ $(CFLAGS)
.PHONY: clean
clean:
rm -f $(OBJS)
For testing purposes I have a single main.cpp in src folder and a random header file in include folder. The error I am getting when running the simple make command is the following:
make: *** No rule to make target `src/obj/%.o', needed by `all'. Stop.
EDIT : With the help of the guys below i came up with the solution
CC=g++
IDIR=include
SDIR=src
ODIR=src/obj
CFLAGS=-Wall -std=c++11 -I$(IDIR)
_DEPS = yo.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
_OBJ = main.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
_SRC = main.cpp
SRC = $(patsubst %,$(SDIR)/%,$(_SRC))
$(ODIR)/%.o: $(SRC) $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
all: $(OBJ)
$(CC) -o run $^ $(CFLAGS) $(LIBS)
.PHONY: clean
clean:
rm -f $(OBJS)
There is a difference in using % in your two cases. When you write:
$(ODIR)/%.o : $(SDIR)/%.cpp $(IDIR)/%.h
that will do pattern substitution, and create a bunch of rules like:
$(ODIR)/foo.o : $(SDIR)/foo.cpp $(SDIR)/foo.h
So it's fine there, although you should use the % explicitly there so it's clear to see what the rule is doing.
But when you use it here:
all : $(ODIR)/%.o
That is literally looking for the target $(ODIR)/%.o for which you don't have a rule. There's no substitution. And you don't have a rule to make that target - hence the error. What you meant to do was have all depend on all the actual objects, for which you'll want to use the wildcard function:
SOURCES = $(wildcard $(SDIR)/*.cpp)
OBJECTS = $(SOURCES:$(SDIR)/%.cpp=$(ODIR)/%.o)
all : $(OBJECTS)
gcc -o run $^ $(CFLAGS)
When you use
OBJS=$(ODIR)/%.o
The %.o part does not expand to anything meaningful. It just remains as the literal value %.o. Same problem exists for DEPS and SRCS as well.
You need to use the wildcard and patsub functions. Instead of
DEPS=$(IDIR)/%.h
OBJS=$(ODIR)/%.o
SRCS=$(SDIR)/%.cpp
use
DEPS=$(wildcard $(IDIR)/*.h)
SRCS=$(wildcard $(SDIR)/*.cpp)
OBJS=$(patsub %.cpp,%.o,$(SRCS))
I know it has already been discussed a lot, but I'm getting a bit crazy and cannot figured it out by myself.
I'm trying to learn how to create makefiles, and I'm having problems in defining a makefile for files in different folders.
This is what I would like to obtain, after compiling:
/makefile
/test.exe
/src/factorials.cpp
/src/main.cpp
/src/hello.cpp
/obj/factorials.o
/obj/main.o
/obj/hello.o
/include/functions.h
What is wrong with this makefile?
C++ = g++
FILENAME = test
SOURCES_PATH = src/
SRC = $(SOURCES_PATH)factorial.cpp $(SOURCES_PATH)main.cpp $(SOURCES_PATH)hello.cpp
OBJ = factorial.o main.o hello.o
all: test.exe
test.exe: $(OBJ)
$(C++) $(OBJ) -o $(FILENAME) -Iinclude
%.o:
$(C++) -c $(SOURCES_PATH)$*.cpp -Iinclude
clean:
rm -f test.exe
Everything goes correctly, but it gives me error trying to compile src/all.cpp. Besides, I don't know how to say to g++ to put .o files into obj/ folder.
Thanks a lot!
You should fix your .o rule as follows
obj/%.o: $(SOURCES_PATH)/%.cpp
$(CC) $(CXXFLAGS) $< -o $#
Alternatively $(vpath) can be used to resolve where make looks up the source (prerequisite) files for a target:
vpath += $(SOURCES_PATH)
obj/%.o: %.cpp
$(CC) $(CXXFLAGS) $< -o $#
So it seems I was able to obtain the result by using the following makefile
C++ = g++
FILENAME = test
OBJS = obj/factorial.o obj/hello.o obj/main.o
INC = -Iinclude/
vpath+= src
$(FILENAME): $(OBJS)
$(C++) $(OBJS) -o $# $(INC)
obj/%.o: %.cpp
$(C++) -o $# -c $< $(INC)
all: $(FILENAME)
clean:
rm -rf objs/*.o *~ $(FILENAME).exe
Thanks! :)
I know many people have asked this before but I haven't been able to resolve it. I want to debug a makefile project in eclipse, but I can't. I'm just learning c++ and don't know how to write makefiles, but my teacher gave me one to use, I have posted it below. How can I fix this error?
Also, if it is of any help to you guys, I only want to debug the DijkstraTest.cpp main function, not any of the other ones.
# first name a variable objects for all object files
# FOR strauss
#CXX = CC
objectsqueue = LinkedList.o
objectstestqueue = QueueTests.o
objectsheap = BinaryHeap.o
objectstestheap = BinaryHeapTest.o
objectsdijkstra = CSV.o Network.o Dijkstra.o
objectstestdijkstra = DijkstraTest.o
# name a variable sources for all source files
sourcesqueue = LinkedList.cpp
sourcestestqueue = QueueTests.cpp
sourcesheap = BinaryHeap.cpp
sourcestestheap = BinaryHeapTest.cpp
sourcesdijkstra = CSV.cpp Network.cpp Dijkstra.cpp
sourcestestdijkstra = DijkstraTest.cpp
# now make default target all exe files
all: testqueue testheap testdijkstra
# list the dependencies for object files - those header files which help build objects
LinkedList.cpp: Collection.h Stack.h Queue.h
QueueTests.o: QueueTests.cpp LinkedList.cpp
BinaryHeap.o: BinaryHeap.h
BinaryHeapTest.o: BinaryHeap.h
Dijkstra.o: CSV.h Dijkstra.h Network.h BinaryHeap.h
# how to build all object files from all dependent source files
$(objectsqueue): $(sourcesqueue)
$(CXX) -c $(sourcesqueue) $(INCLUDES)
$(objectstestqueue): $(sourcestestqueue)
$(CXX) -c $(sourcestestqueue) $(INCLUDES)
$(objectsheap): $(sourcesheap)
$(CXX) -c $(sourcesheap) $(INCLUDES)
$(objectstestheap): $(sourcestestheap)
$(CXX) -c $(sourcestestheap) $(INCLUDES)
$(objectsdijkstra): $(sourcesdijkstra)
$(CXX) -c $(sourcesdijkstra) $(INCLUDES)
$(objectstestdijkstra): $(sourcestestdijkstra)
$(CXX) -c $(sourcestestdijkstra) $(INCLUDES)
clean:
rm -f *.o
rm -f *.exe
testqueue: $(objectsqueue) $(objectstestqueue)
$(CXX) -o QueueTests.exe $(objectsqueue) $(objectstestqueue)
testheap: $(objectsheap) $(objectstestheap)
$(CXX) -o BinaryHeapTest.exe $(objectsheap) $(objectstestheap)
testdijkstra: $(objectsheap) $(objectsdijkstra) $(objectstestdijkstra)
$(CXX) -o DijkstraTest.exe $(objectsheap) $(objectsdijkstra) $(objectstestdijkstra)
To be able to debug an application, you need to compile it using the -g (debug) flag:
CXXFLAGS=-g
$(objectsqueue): $(sourcesqueue)
$(CXX) $(CXXFLAGS) -c $(sourcesqueue) $(INCLUDES)
...
testqueue: $(objectsqueue) $(objectstestqueue)
$(CXX) $(CXXFLAGS) -o QueueTests.exe $(objectsqueue) $(objectstestqueue)
....
you need to use this flag for all compilation rules.
I am new to makefiles. I have a makefile, I want it generated a shared library from more than one .cpp files. But the following makefile only generated different .so based on the same .cpp file. Can anyone help?
SRC_DIR = $(PROJECT_BASE_DIR)/src
SRCFILES = $(wildcard $(SRC_DIR)/*.cpp)
OBJFILES = $(patsubst $(SRC_DIR)/%.cpp,$(BUILD_TARGET_DIR)/%.$(OBJ_EXTENSION),$(SRCFILES))
...
ifeq ($(OS),$(OS_LINUX))
$(CLIENTLIB): $(OBJFILES)
gcc $(CXXFLAGS) -o $# $< $(LINKER_FLAGS)
$(OBJFILES): $(SRCFILES) ==> I believe this is the line with problem.
gcc $(CXXFLAGS) -c -o $# $<
Currently you're trying to convert all .cpp files to all .o files in one compilation step.
Change:
$(OBJFILES): $(SRCFILES) ==> I believe this is the line with problem.
gcc $(CXXFLAGS) -c -o $# $<
to:
%.$(OBJ_EXTENSION): %.cpp
gcc $(CXXFLAGS) -c -o $# $<
These are the rules I use in my makefile and they work, hope it can help you
CFILES = $(wildcard *.c)
OBJS = $(CFILES:%.c=%.o)
%.o: %.c
$(CC) $(CFLAGS) -I$(INCLUDE) $< -o $#
I've got this Makefile:
CFLAGS = -c -Wall
CC = g++
EXEC = main
SOURCES = main.cpp listpath.cpp Parser.cpp
OBJECTS = $(SOURCES: .cpp=.o)
EXECUTABLE = tp
DIR_SRC = /src/
DIR_OBJ = /obj/
all: $(SOURCES) $(OBJECTS)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $#
.cpp.o:
$(CC) $(CFLAGS) $< -o $#
clean:
rm $(OBJECTS) $(EXECUTABLE)
Note this:
I'm in the directory "." which contains the makefile
The folder "./src" EXISTS, and has all the .h and .cpp files
The folder "./obj" doesn't exist, I want makefile to create it and put all the .o there
The error I get is:
No rules to build "main.cpp", necessary for "all". Stopping.
Help!
All right, from the top:
CFLAGS = -c -Wall
CC = g++
# EXEC = main never used, not needed
SOURCES = main.cpp listpath.cpp Parser.cpp
So far, so good. Note that this SOURCES doesn't mention DIR_SRC, so we'll have to make that connection later (and $(DIR_SRC)$(SOURCES) won't work, because the path must be appended to each member of the list). But OBJECTS really needs paths (e.g. /obj/main.o):
OBJECTS = $(patsubst %.cpp, $(DIR_OBJ)%.o, $(SOURCES))
EXECUTABLE = tp
DIR_SRC = /src/
DIR_OBJ = /obj/
(Personally I don't like putting the trailing slash in the variable, but it's a matter of taste.) The first target is the default target, so it should build what you actually want built:
all: $(EXECUTABLE)
Don't worry about listing the sources as prerequisites; they will sort themselves out later.
$(EXECUTABLE): $(OBJECTS)
$(CC) $(CFLAGS) $^ -o $# # <-- note the automatic variable $^
The .cpp.o convention doesn't really work here; we'll have to spell it out. And we must tell Make to search $(DIR_SRC) for .cpp files:
$(OBJECTS): $(DIR_OBJ)%.o: %.cpp $(DIR_OBJ)
$(CC) $(CFLAGS) $< -o $#
$(DIR_OBJ):
mkdir $#
vpath %.cpp $(DIR_SRC)
And tell Make that clean is not a real target, just to be safe:
.PHONY: clean
clean:
rm $(OBJECTS) $(EXECUTABLE)
EDIT:
I shouldn't have attempted so much in one step. Let's try something simpler:
$(DIR_OBJ)%.o: $(DIR_SRC)%.cpp $(DIR_OBJ)
$(CC) $(CFLAGS) $< -o $#
Edit the SOURCES to include the source directory (e.g. src/main.cpp etc.).
For the object files, consider something like this:
OBJECTS = $(subst src/,obj/,$(SOURCES:%.cpp=%.o))
# ...
all: $(SOURCES) build
.PHONY: build
build: pre_build $(EXECUTABLE)
.PHONY: pre_build
pre_build: obj
obj:
-mkdir obj
$(EXECUTABLE): $(OBJECTS)
$(CC) $(CFLAGS) $^ -o $#