Makefile always recompiles - c++

Question

i am having a hard time with the Makefile below. It always recompiles because it is looking for the objects in "source/" instead of "objects/".
Since i did not write that Makefile and don't know what all those options mean i can't figure out how to tell it to look for the objects in the correct folder.
TITLE =example_title
SRC_DIR = source/
OBJ_DIR = objects/
OUTDIR = build/
SRC := $(wildcard **/*.cpp)
OBJ := $(patsubst source/%.cpp,%.o,$(SRC))
FP_OBJ := $(patsubst %,objects/%,$(OBJ))
LIB = $(wildcard *.a) $(wildcard **/*.a)
CC =g++
LD =g++
CC_FLAGS = -m32 -c -Wall -g -o
EXECUTABLE = $(TITLE)
LD_FLAGS = -m32 -L/usr/lib32 -o $(OUTDIR)$(EXECUTABLE)
$(OUTDIR)$(EXECUTABLE) : $(OBJ)
$(LD) $(LD_FLAGS) $(FP_OBJ) $(LIB)
$(OBJ) : $(SRC)
$(CC) $(CC_FLAGS)$(OBJ_DIR)$# $(SRC_DIR)$*.cpp
$(TITLE).tar.gz : **/*.h **/*.cpp Makefile **/*.txt
tar -czf $# Makefile **/*.h **/*.cpp **/*.txt
dist: $(TITLE).tar.gz
all : $(OUTDIR)$(EXECUTABLE)
clean :
rm -f $(OBJ_DIR)*.o
rm -f $(OUTDIR)$(EXECUTABLE) $(TITLE).tar.gz

Answer 1

This should do it:
$(OUTDIR)$(EXECUTABLE) : $(FP_OBJ)
$(LD) $(LD_FLAGS) $^ $(LIB)
$(FP_OBJ) : $(OBJ_DIR)%.o : $(SRC_DIR)%.cpp
$(CC) $(CC_FLAGS) $# $<
The basic problem was here:
$(OBJ) : $(SRC)
$(CC) $(CC_FLAGS)$(OBJ_DIR)$# $(SRC_DIR)$*.cpp
Apart from the fact that $(OBJ) : $(SRC) makes each object depend on all sources, this rule promises foo.o and delivers objects/foo.o. So every time through, Make saw that there was no foo.o, and duly tried to rebuild it and the executable that required it.
There are other problems with this makefile, like the sloppy wildcards and the obnoxious practice of including slashes in the directory names, but they're not so serious.