Expecting a left parenthesis ('(') [12.1.3.3(IEEE 2001)] - if-statement

Question

I keep getting the following log:
file: lab1.v
if (in1 == 1)
|
ncvlog: *E,EXPLPA (lab1.v,25|1): expecting a left parenthesis ('(') [12.1.3.3(IEEE 2001)].
(#1 y = 1'b1;
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ncvlog: *E,EXPENM (lab1.v,26|1): expecting the keyword 'endmodule' [12.1(IEEE)].
module worklib.ex1:v
errors: 2, warnings: 0
ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 2).
for the following code:
module ex1 (in1, in2 ,clk , out1 , out2, bus);
//input&outputs
//==============
input in1,in2,clk;
output out1,out2,bus;
//reg
//====
reg out1= 1'b0, out2=1'b0, y=1'b0 ;//y = previos state
reg [2:0] bus=3'b000;
//on clk pose edge
//=================
always #(posedge clk) begin
if ((in1==1)&&(y==0))
out1=1;
else if ((in1==0)&&(y==1))
out2 = 1;
else
out1 = 0;
out2 = 0;
end if
if (in1 == 1)
#1 y = 1'b1;
else if (in1 == 0)
#1 y = 1'b0;
end if
if((negedge in2)&&(in1==1))
bus = 3'b001;
else if ((negedge in2)&&(in1==0))
bus = 3'b000;
else
bus <= bus + 1;
end if
end
endmodule

Answer 1

In Verilog, use begin ... end for scoping.
if ((in1==1)&&(y==0))
out1=1;
else if ((in1==0)&&(y==1))
out2 = 1;
else
out1 = 0;
out2 = 0;
end if
should be rewritten as
if ((in1==1)&&(y==0))
out1=1;
else if ((in1==0) && (y==1))
out2=1;
else
begin
out1 = 0;
out2 = 0;
end
Other if ... else ... end if blocks should be rewritten similarly. end if does not work in Verilog.