C++ - Makefile using g++ - c++

I have made a Makefile for my CMSC 202 course project, 'Blackjack'. It does everything I need it to and it works perfectly. You may be asking why I posted here then, this is because I have no idea how it works and I didn't use any other resources but myself to create it.
Here is my Makefile code.
# Object files to either reference or create
OBJECTS = Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
# The executable file that will be created at the end
EXEC = Proj2.out
# The flags to use for compilation
FLAGS = -Wall
# The code compiler to use for compilation
CC = g++
# Perform action on all object files (May or may not exist)
all: $(OBJECTS)
$(CC) $(FLAGS) -o $(EXEC) $(OBJECTS)
Here is the terminal output when I call make in the terminal.
g++ -c -o Proj2.o Proj2.cpp
g++ -c -o Blackjack.o Blackjack.cpp
g++ -c -o Deck.o Deck.cpp
g++ -c -o Card.o Card.cpp
g++ -c -o Hand.o Hand.cpp
g++ -c -o Player.o Player.cpp
g++ -Wall -o Proj2.out Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
Can anyone tell me how the .o files are being compiled? It does not look like they are being prompted to be compiled with that g++ -c -o $.o $.cpp command anywhere in the Makefile. Nor did I state to use any .cpp files.
Thank you in advance for your help.
Edit
Thanks to all your great help, this is now the terminal output I receive when using make.
g++ -Wall -c -o Proj2.o Proj2.cpp
g++ -Wall -c -o Blackjack.o Blackjack.cpp
g++ -Wall -c -o Deck.o Deck.cpp
g++ -Wall -c -o Card.o Card.cpp
g++ -Wall -c -o Hand.o Hand.cpp
g++ -Wall -c -o Player.o Player.cpp
g++ -Wall -o Proj2.out Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
Thank you so much to all of you who have contributed.

Make has a set of implicit rules (see here for a reference). For instance
Compiling C++ programs
`n.o' is made automatically from `n.cc' or `n.C' with a command of the form
`$(CXX) -c $(CPPFLAGS) $(CXXFLAGS)'.
Most make's will also use this rule for .cpp files.
When make sees there's a x.o requirement for one of your targets, it will try to see if it can generate x.o using implicit rules, and in your case find it can do it starting from a .cpp file.

This Makefile uses implicit rules which are a great way to reduce duplication.
By default the first target will be built, here all. It depends on a number
of object files listed in a variable $OBJECTS, e.g. Proj2.o who's
dependencies aren't listed in the Makefile. Now if make sees an input file in the current directory
with a matching name, e.g. Proj2.cpp it will try
to build Proj2.o from it (there are other implicit rules for sources in
other languages). Proj2.o would then be built by default with the command
$(CXX) $(CXXFLAGS) -c -o Proj2.o
where $(CXX) the name of the C++ compiler (g++ in your case).
The explicit build step for all assembles all the object files into the
target executable.
Looking at above build command you'll notice a small problem in your Makefile. Since the flags to the C++ compiler are given in a variable FLAGS and not the standard CXXFLAGS no warnings will be emitted when building the object files. Using the standard name would fix this (you do want warnings, maybe even more than -Wall gives you).

Related

First Makefile Questions: No rule to make target

I'm attempting to create my first ever Makefile and looking for the most simple, understandable version--even if it isn't "good practice." I'll deal with that at a later time. :)
Basically, I just want to run make in the command line and have it execute the several g++ commands so I don't have to. For example, instead of entering the following (at top level dir) in the command line...
$g++ -c ./src/RaspPi4Main.cpp -o ./src/RaspPi4Main.o
$g++ -c ./src/funcI2cCom/funcI2cCom.cpp -o ./src/funcI2cCom/funcI2cCom.o
$g++ -o ./bin/RaspPi4Main ./src/RaspPi4Main.o ./src/funcI2cCom/funcI2cCom.o -lwiringPi
...I'd like something similar to my attempt at a Makefile:
RaspPi4Main: RaspPi4Main.o funcI2cCom.o (and all header files? or not needed if added below?)
g++ -o ./bin/RaspPi4Main ./src/RaspPi4Main.o ./src/funcI2cCom/funcI2cCom.o -lwiringPi
RaspPi4Main.o: RaspPi4Main.cpp
g++ -c ./src/RaspPi4Main.cpp -o ./src/RaspPi4Main.o
funcI2cCom.o: funcI2cCom.cpp funcI2cCom.h
g++ -c ./src/funcI2cCom/funcI2cCom.cpp -o ./src/funcI2cCom/funcI2cCom.o
Hopefully, I'm close? Thanks!
As a first step, you need to make sure your recipes produce their target and that inputs are either files or targets of other rules:
bin/RaspPi4Main: src/RaspPi4Main.o src/funcI2cCom/funcI2cCom.o
g++ -o bin/RaspPi4Main src/RaspPi4Main.o src/funcI2cCom/funcI2cCom.o -lwiringPi
src/RaspPi4Main.o: src/RaspPi4Main.cpp
g++ -c src/RaspPi4Main.cpp -o src/RaspPi4Main.o
src/funcI2cCom/funcI2cCom.o: src/funcI2cCom/funcI2cCom.cpp src/funcI2cCom/funcI2cCom.h
g++ -c src/funcI2cCom/funcI2cCom.cpp -o src/funcI2cCom/funcI2cCom.o
Note that this is quite verbose. You can shorten it quite significantly by making use of automatic variables. Concretely, $# is the name of the target, $< is the name of the first dependency, and $^ are all dependencies:
bin/RaspPi4Main: src/RaspPi4Main.o src/funcI2cCom/funcI2cCom.o
g++ -o $# $^ -lwiringPi
src/RaspPi4Main.o: src/RaspPi4Main.cpp
g++ -c $< -o $#
src/funcI2cCom/funcI2cCom.o: src/funcI2cCom/funcI2cCom.cpp src/funcI2cCom/funcI2cCom.h
g++ -c $< -o $#
Note that there's quite some repetition. Luckily, Make already knows how to compile a .cpp file into a .o file through implicit rules. Thus you can omit the recipes for these rules:
bin/RaspPi4Main: src/RaspPi4Main.o src/funcI2cCom/funcI2cCom.o
g++ -o $# $^ -lwiringPi
src/RaspPi4Main.o: src/RaspPi4Main.cpp
src/funcI2cCom/funcI2cCom.o: src/funcI2cCom/funcI2cCom.cpp src/funcI2cCom/funcI2cCom.h

Makefile with pthread won't compile properly with multiple versions

For a project, I have to create a simple makefile for the source code which includes pthreads and command line arguments (if those matter to include).
The first version of the makefile that didn't work was this:
mr: mr.o
g++ -std=c++11 -pthread mr.o -o mr
mr.o: mapred.cc
g++ -std=c++11 -pthread -c mapred.cc
clean:
rm *.o mr
and I got the following error that the object file did not exist?
So then I decided to flip the two first statements around:
mr.o: mapred.cc
g++ -std=c++11 -pthread -c mapred.cc
mr: mr.o
g++ -std=c++11 -pthread mr.o -o mr
clean:
rm *.o mr
and it compiles, sort of? All I get in the terminal is:
g++ -std=c++11 -pthread -c mapred.cc
and nothing else. When I look at what files were created, all I see is a new file mapred.o created but no executable. So no errors but not fully completed. If you guys have any tips to help me out that would be very appreciated. Thank you!
If you don't specify an explicit output name with the -o option, then the compiler will name object file the same as the source file but with an .o suffix.
In your case, the command
g++ -std=c++11 -pthread -c mapred.cc
will create an object file named mapread.o.
Either use mapread.o for your target names and when linking, or use the -o option:
g++ -std=c++11 -pthread -c mapred.cc -o mr.o
As for your second problem, unless you specify an explicit target when invoking make, it will only use the first target and nothing else.

Boost & makefile

i'm trying to use the boost_math libs on OS X (i'm not using Xcode), specifically the one containing the error function
I downloaded and compiled boost_1_60_0 myself (using bootstrap.sh and following the instructions.) I didn't use home-brew or something else, which might be why my installation seems so screwed up.
What i'm trying to include in my Szabo.hpp is this:
#include <boost/math/special_functions/erf.hpp>
My makefile goes like this:
LIB_FLAGS = -L/Documents/boost_1_60_0/stage/lib -lboost_math
ALL_OBJECTS = main.o Gaussienne.o Grille.o Szabo.o
all: $(ALL_OBJECTS)
g++ -o hydrogene $(ALL_OBJECTS) $(LIB_FLAGS)
Gaussienne.o: Gaussienne.cpp
g++ -o Gaussienne.o -c Gaussienne.cpp -W -Wall -ansi
main.o: Gaussienne.hpp Grille.hpp main.cpp Szabo.o
g++ -o main.o -c main.cpp -W -Wall -ansi
Grille.o: Grille.cpp Gaussienne.cpp
g++ -o Grille.o -c Grille.cpp -W -Wall -ansi
Szabo.o: Szabo.cpp Gaussienne.cpp
g++ -o Szabo.o -c Szabo.cpp -W -Wall -ansi
clean:
rm -rf *.o
mrproper: clean
rm -rf hydrogene
I get no linking error from g++, however i got:
In file included from Szabo.cpp:12:
./Szabo.hpp:21:10: fatal error: 'boost/math/special_functions/erf.hpp' file not found
#include <boost/math/special_functions/erf.hpp>
^
1 error generated.
Can you please provide help on how to fix this? Thanks in advance
Ok so apparently likes this, it works:
LIB_FLAGS = -L/Users/devolution/Documents/boost_1_60_0/stage/lib -lboost_math_tr1
I_FLAGS = -I/Users/devolution/Documents/boost_1_60_0/
ALL_OBJECTS = main.o Gaussienne.o Grille.o Szabo.o
all: $(ALL_OBJECTS)
g++ -o hydrogene $(ALL_OBJECTS) $(LIB_FLAGS)
Gaussienne.o: Gaussienne.cpp
g++ -o Gaussienne.o -c Gaussienne.cpp -ansi ${I_FLAGS}
main.o: Gaussienne.hpp Grille.hpp main.cpp Szabo.o
g++ -o main.o -c main.cpp -ansi ${I_FLAGS}
Grille.o: Grille.cpp Gaussienne.cpp
g++ -o Grille.o -c Grille.cpp -ansi ${I_FLAGS}
Szabo.o: Szabo.cpp Gaussienne.cpp
g++ -o Szabo.o -c Szabo.cpp -ansi ${I_FLAGS}
.PHONY: clean mrproper
clean:
rm -rf *.o
mrproper: clean
rm -rf hydrogene
Is there a way to pass I_FLAGS?
You've compiled Boost's separately-compiled libraries, which is great, but you didn't copy the headers to your toolchain's include path. Indeed, most of Boost is comprised of header-only libraries, so this is arguably the more crucial step of installing Boost.
The internet tells me you may be able to find the default header search path with the following command at shell:
gcc -x c++ -v -E /dev/null
(https://stackoverflow.com/a/19852298/560648)
When you find it, copy the distribution's boost subdirectory to it.
And, yes, having home-brew install Boost for you would have been much easier… probably one command!

C++ - Makefile Good Practice

I have a Makefile that works for how I'm using it, but will anyone tell me if what I'm doing is good practice? Or if there is a better, cleaner or more efficient way to achieve the goal I am reaching?
Here is my Makefile Code.
# Object files to either reference or create
OBJECTS = Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
# The executable file that will be created
EXEC = Proj2.out
# The c++ flags to use for compilation
CXXFLAGS = -Wall
# The c++ compiler to use for compilation
CXX = g++
# This section is called on 'make'
# Will call compile, and then call clean
all: compile clean
# Perform action on all object files (May or may not exist)
# The makefile will implicitly compile all .o files needed
# Will also compile them into the EXEC file listed
compile: $(OBJECTS)
$(CXX) $(CXXFLAGS) -o $(EXEC) $(OBJECTS)
# This section is called after compilation is completed
# This will clean all existing .o files listed in the directory
clean:
rm -f *.o
Here is the terminal output when I call make.
g++ -Wall -c -o Proj2.o Proj2.cpp
g++ -Wall -c -o Blackjack.o Blackjack.cpp
g++ -Wall -c -o Deck.o Deck.cpp
g++ -Wall -c -o Card.o Card.cpp
g++ -Wall -c -o Hand.o Hand.cpp
g++ -Wall -c -o Player.o Player.cpp
g++ -Wall -o Proj2.out Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
rm -f *.o
Is it good practice to use a Makefile like this? Specifically, am I doing the cleaning part of my Makefile correctly?
You should not make all depend on clean at all. By doing this you are ensuring that every time you run make, you have to recompile everything. If you want to do that then using make is itself useless: just write a shell script that compiles and links your code.
The clean target should be a separate target and if you want to clean your workspace you run make clean explicitly.
The other problem with your makefile is that the link rule lists compile as the target, but it builds $(EXE). It's almost never a good idea to have a rule create a file which is not exactly the target you told make it would build. To ensure this, always use $# as the target to generate. Rewrite it like this:
compile: $(EXE)
$(EXE): $(OBJECTS)
$(CXX) $(CXXFLAGS) -o $# $^

makefile auto removing .o files

I am taking a C++ course in college and they want us to manually type in all of the test files... I know, however, that there is a way to do it with out, which is how I ended up with the current(http://pastebin.com/6d9UtKM4) makefile. My question is, why is this makefile automatically removing all the .o files it uses for compiling when it is done? It's not killing me, but I would like to preserve the .o files. I have pasted the makefile here(http://pastebin.com/6d9UtKM4). I have also pasted the current result of running "make tests" here(http://pastebin.com/h3Ny3dib). (Note the part at the bottom of that page that removes all the .o files automatically.)
I would also like to be able to make it generate it like this:
g++ -o compileDir/assembler.o -c -Wall src/assembler.cpp
g++ -o compileDir/string.o -c -Wall src/string.cpp
g++ -c -Wall -o compileDir/test_assignment.o testSrc/test_assignment.cpp
g++ -o testDir/test_assignment compileDir/test_assignment.o compileDir/string.o compileDir/assembler.o
g++ -c -Wall -o compileDir/test_bracket.o testSrc/test_bracket.cpp
g++ -o testDir/test_bracket compileDir/test_bracket.o compileDir/string.o compileDir/assembler.o
testDir/test_bracket
testDir/test_assignment
In other words, I want it to compile everything, then run everything. I hope this isn't too much to ask!
Edit: Additional Information: (This is the code that does "make tests")
tests: assembler.o string.o $(test_output) $(test_stringOutput)
#echo '--- Testing complete ---'
$(testDir)%: $(compileDir)%.o string.o
g++ -o $# $< $(compileDir)string.o $(compileDir)assembler.o
$#
#echo ''
$(compileDir)%.o: $(testSourceDir)%.cpp
g++ -c -Wall -o $# $<
$(compileDir)%.o: $(testStringSrc)%.cpp
g++ -c -Wall -o $# $<
EDIT: -----------------------------------------
Resolved via comments:
Adding this line fixed it:
.PRECIOUS $(compileDir)%.o
You might add
.PRECIOUS: %.o
which should be implicit, but perhaps you've got a weird setup.
Make treats your .o files as intermediate and removes them. You can prevent automatic deletion of those by adding them a dependency of the special .SECONDARY target. See Chains of Implicit Rules for more details. Good luck!