Beginner Sublime & C++ Linker Setup - c++

I am trying to use Sublime Text 2 as my IDE. I am setting up a project but having difficulty understanding how to properly link files. When I build off of assn1.cpp, I get the following error:
C:\Users\..\AppData\Local\Temp\ccEffTCN.o:assn1.cpp:(.text+0xdd): undefined reference to `SceneData::SceneData(int)'
collect2.exe: error: ld returned 1 exit status
Here is my main cpp file. I remove the code that isn't causing the problem for the sake of clarity. I do not get a build error if I comment out where I instantiate a new Scene Data object.
#include "SceneData.h"
using namespace std;
int main(int argc, char* argv[]){
SceneData sc = SceneData(1);
return 0;
}
For reference, here is my h and cpp file for SceneData.
// SceneData.cpp
#include "SceneData.h"
SceneData::SceneData(int x){
temp = x;
}
int SceneData::publicTemp(){
return 0;
}
#ifndef SCENEDATA_H
#define SCENEDATA_H
class SceneData{
int temp;
public:
SceneData(int x);
int publicTemp();
};
#endif // SCENEDATA_H
I am using the sublime provided c++ build config. mingw and g++ are installed. I have all of the files saved in the correct project directory. My specific question is what am I missing to ensure files are linked when I create the o files that end up in the executable?
** Edits Below *******
This is my make file
OBJS = $(patsubst %.c, %.o, $(wildcard *.c)) \
$(patsubst %.cpp, %.o, $(wildcard *.cpp)) \
$(patsubst %.cxx, %.o, $(wildcard *.cxx))
CFLAGS = -Wall
CXXFLAGS = -Wall
OPT = -O4
balls2.png:
%.png: %.ppm
convert $< $#
%.ppm: %.nff trace
./trace < $*.nff
mv trace.ppm $#
trace: $(OBJS)
$(CXX) $(OPT) -o $# $(OBJS) $(LDFLAGS) $(LDLIBS)
%.o: %.c
$(CC) $(OPT) -c -o $# $(CFLAGS) $<
%.o: %.cxx
$(CXX) $(OPT) -c -o $# $(CXXFLAGS) $<
%.o: %.cxx
$(CXX) $(OPT) -c -o $# $(CXXFLAGS) $<
clean:
rm -f *.o
clobber: clean
rm -f trace *.ppm *.png
assn1.o: assn1.cpp SceneData.h
SceneData.o: SceneData.cpp SceneData.h

I had no problem compiling your code with g++, using Sublime as my text editor. Are you using a make file when compiling? If so, please post your make file code. Without a make file, I just needed to enter:
g++ *.cpp
And then ./a.out gave me the output '0' as expected.
Perhaps the following thread may be of assistance to you: Can't build C++ program using Sublime Text 2

Related

Error when executing make

I am trying to create a makefile for my project, but i seem to run into some errors, as I am testing new things. My file structure is as such:
~/main #root project folder
~/main/include #header files (mostly class headers)
~/main/src #source files
~/main/src/obj #object files
Makefile
(Makefile is in the root project folder)
Makefile:
CC=g++
IDIR=include
SDIR=src
ODIR=src/obj
DEPS=$(IDIR)/%.h
OBJS=$(ODIR)/%.o
SRCS=$(SDIR)/%.cpp
CFLAGS=-Wall -std=c++11 -I$(IDIR)
$(OBJS): $(SRCS) $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
all: $(OBJS)
gcc -o run $^ $(CFLAGS)
.PHONY: clean
clean:
rm -f $(OBJS)
For testing purposes I have a single main.cpp in src folder and a random header file in include folder. The error I am getting when running the simple make command is the following:
make: *** No rule to make target `src/obj/%.o', needed by `all'. Stop.
EDIT : With the help of the guys below i came up with the solution
CC=g++
IDIR=include
SDIR=src
ODIR=src/obj
CFLAGS=-Wall -std=c++11 -I$(IDIR)
_DEPS = yo.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
_OBJ = main.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
_SRC = main.cpp
SRC = $(patsubst %,$(SDIR)/%,$(_SRC))
$(ODIR)/%.o: $(SRC) $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
all: $(OBJ)
$(CC) -o run $^ $(CFLAGS) $(LIBS)
.PHONY: clean
clean:
rm -f $(OBJS)
There is a difference in using % in your two cases. When you write:
$(ODIR)/%.o : $(SDIR)/%.cpp $(IDIR)/%.h
that will do pattern substitution, and create a bunch of rules like:
$(ODIR)/foo.o : $(SDIR)/foo.cpp $(SDIR)/foo.h
So it's fine there, although you should use the % explicitly there so it's clear to see what the rule is doing.
But when you use it here:
all : $(ODIR)/%.o
That is literally looking for the target $(ODIR)/%.o for which you don't have a rule. There's no substitution. And you don't have a rule to make that target - hence the error. What you meant to do was have all depend on all the actual objects, for which you'll want to use the wildcard function:
SOURCES = $(wildcard $(SDIR)/*.cpp)
OBJECTS = $(SOURCES:$(SDIR)/%.cpp=$(ODIR)/%.o)
all : $(OBJECTS)
gcc -o run $^ $(CFLAGS)
When you use
OBJS=$(ODIR)/%.o
The %.o part does not expand to anything meaningful. It just remains as the literal value %.o. Same problem exists for DEPS and SRCS as well.
You need to use the wildcard and patsub functions. Instead of
DEPS=$(IDIR)/%.h
OBJS=$(ODIR)/%.o
SRCS=$(SDIR)/%.cpp
use
DEPS=$(wildcard $(IDIR)/*.h)
SRCS=$(wildcard $(SDIR)/*.cpp)
OBJS=$(patsub %.cpp,%.o,$(SRCS))

Makefile on different folders

I know it has already been discussed a lot, but I'm getting a bit crazy and cannot figured it out by myself.
I'm trying to learn how to create makefiles, and I'm having problems in defining a makefile for files in different folders.
This is what I would like to obtain, after compiling:
/makefile
/test.exe
/src/factorials.cpp
/src/main.cpp
/src/hello.cpp
/obj/factorials.o
/obj/main.o
/obj/hello.o
/include/functions.h
What is wrong with this makefile?
C++ = g++
FILENAME = test
SOURCES_PATH = src/
SRC = $(SOURCES_PATH)factorial.cpp $(SOURCES_PATH)main.cpp $(SOURCES_PATH)hello.cpp
OBJ = factorial.o main.o hello.o
all: test.exe
test.exe: $(OBJ)
$(C++) $(OBJ) -o $(FILENAME) -Iinclude
%.o:
$(C++) -c $(SOURCES_PATH)$*.cpp -Iinclude
clean:
rm -f test.exe
Everything goes correctly, but it gives me error trying to compile src/all.cpp. Besides, I don't know how to say to g++ to put .o files into obj/ folder.
Thanks a lot!
You should fix your .o rule as follows
obj/%.o: $(SOURCES_PATH)/%.cpp
$(CC) $(CXXFLAGS) $< -o $#
Alternatively $(vpath) can be used to resolve where make looks up the source (prerequisite) files for a target:
vpath += $(SOURCES_PATH)
obj/%.o: %.cpp
$(CC) $(CXXFLAGS) $< -o $#
So it seems I was able to obtain the result by using the following makefile
C++ = g++
FILENAME = test
OBJS = obj/factorial.o obj/hello.o obj/main.o
INC = -Iinclude/
vpath+= src
$(FILENAME): $(OBJS)
$(C++) $(OBJS) -o $# $(INC)
obj/%.o: %.cpp
$(C++) -o $# -c $< $(INC)
all: $(FILENAME)
clean:
rm -rf objs/*.o *~ $(FILENAME).exe
Thanks! :)

Makefile for cross compilation linux

I have been asked to port our product into another application.(our s/w is running on linux virtualbox)
I have got a directory of their interface files and also a example code on trying to configure their software/hardware. I see their interface files under the s/w directory. In the reference code directory, I see a makefile with the reference to their reference code.
Trying to run their reference code makefile. getting error that
make: *** No rule to make target `../ main.o" :(
Btw donot understand why SIMUDIR = -I\..\custom_simcode\ this is done in the makefile ?
Also not much familiar with crosscompiler syntax !
ifndef CROSS_CC_PREFIX
CROSS_CC_PREFIX=$(CROSS_COMPILE)
endif
PROGRAM = customer_sim
CC=$(CROSS_CC_PREFIX)gcc
LD=$(CROSS_CC_PREFIX)ld
RANLIB=$(CROSS_CC_PREFIX)corelib
CFLAGS= -g
all: $(PROGRAM)
## Include path
SIMUDIR = -I\..\custom_simcode\
CUST_INT_INC = -I./../cust_Intf/DecHandler/inc \
-I./../CCPU
LIBDIR = -L./../cust_Intf \
-L./../cust_IntfApi
LIBS = -lpthread -customercif -customerapi
LDFLAGS= $(LIBDIR) $(LIBS)
SOURCE = ./../custom_simcode/main.c \
./../custom_simcode/custcode_primitives_init.c \
./../custom_simcode/custccp_primitives_init.c
CFLAGS += $(SIMUDIR) $(CUST_INT_INC) -DPRINT_IO_CONSOLE -UADAPT_CCPU_CUSTIF
OBJS = $(SOURCE:.c=.o)
$(PROGRAM): $(OBJS)
$(CC) -o $# $(OBJS) $(LDFLAGS)
main.o: $(SIMUDIR)/main.c $(SIMUDIR) $(CUST_INT_INC)
$(CC) -c -o /main.o $(SIMUDIR)/main.c
clean:
-rm -f $(OBJS) $(OBJS) $(PROGRAM)
Your $(OBJS) list dependencies for $(PROGRAMs) with directories included but your rule for main.o doesn't have same path.
It would be better to have a generic rule to compile C files like
%.o: %.c
$(CC) -c -o $# $<
Then simply assign extra dependencies for each file like:
$(OBJS): $(SIMUDIR) $(CUST_INT_INC)

building program with make and automatic dependencies

I have written a simple C++ program, and for the first time I want to compile and link it using a makefile. As a challenge I want to make a makefile, which lists all dependencies by itself. I am following this tutorial. My program consist of main.cpp, ext1.cpp and ext1.h. Following the tutorial, I have the following makefile
VPATH = src include
CPPFLAGS = -o include
CC = gcc
SOURCES = main.cpp \
ext1.cpp
-include $(subst .c,.d,$(SOURCES))
%.d: %.c
$(CC) -M $(CPPFLAGS) $< > $#.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
When I run this I get the message: make: *** No targets specified and no makefile found. Stop. It is not clear to me what I am missing in my case?
You are trying to do too much at once.
Step 1. Your first makefile should build the executable without attempting automatic dependency detection.
VPATH = include src
CPPFLAGS += -Iinclude
CC = gcc
exec: main.o ext1.o
$(CC) $^ -o $#
%.o: %.cc
$(CC) -c $(CPPFLAGS) $< -o $#
main.o ext1.o: ext1.h
Step 2. Once that works perfectly, you can put the header dependencies in separate files:
makefile:
VPATH = include src
CPPFLAGS += -Iinclude
CC = gcc
exec: main.o ext1.o
$(CC) $^ -o $#
%.o: %.cc
$(CC) -c $(CPPFLAGS) $< -o $#
-include *.d
main.d:
main.o : ext1.h
ext1.d:
ext1.o: ext1.h
Step 3. Once that works perfectly, you can generate the dependency files automatically:
VPATH = include src
CPPFLAGS += -Iinclude
CC = gcc
exec: main.o ext1.o
$(CC) $^ -o $#
%.o: %.cc
$(CC) -c -MMD $(CPPFLAGS) $< -o $#
-include *.d
no make file found ? what name you have given for makefile? make sure its makefile or Makefile if you are just executing command make else you can pass file name to make like this
make -f yourmakefile
and changes suggested by Petr Budnik must work

No source available for "main()" error for c++ in Eclipse

I know many people have asked this before but I haven't been able to resolve it. I want to debug a makefile project in eclipse, but I can't. I'm just learning c++ and don't know how to write makefiles, but my teacher gave me one to use, I have posted it below. How can I fix this error?
Also, if it is of any help to you guys, I only want to debug the DijkstraTest.cpp main function, not any of the other ones.
# first name a variable objects for all object files
# FOR strauss
#CXX = CC
objectsqueue = LinkedList.o
objectstestqueue = QueueTests.o
objectsheap = BinaryHeap.o
objectstestheap = BinaryHeapTest.o
objectsdijkstra = CSV.o Network.o Dijkstra.o
objectstestdijkstra = DijkstraTest.o
# name a variable sources for all source files
sourcesqueue = LinkedList.cpp
sourcestestqueue = QueueTests.cpp
sourcesheap = BinaryHeap.cpp
sourcestestheap = BinaryHeapTest.cpp
sourcesdijkstra = CSV.cpp Network.cpp Dijkstra.cpp
sourcestestdijkstra = DijkstraTest.cpp
# now make default target all exe files
all: testqueue testheap testdijkstra
# list the dependencies for object files - those header files which help build objects
LinkedList.cpp: Collection.h Stack.h Queue.h
QueueTests.o: QueueTests.cpp LinkedList.cpp
BinaryHeap.o: BinaryHeap.h
BinaryHeapTest.o: BinaryHeap.h
Dijkstra.o: CSV.h Dijkstra.h Network.h BinaryHeap.h
# how to build all object files from all dependent source files
$(objectsqueue): $(sourcesqueue)
$(CXX) -c $(sourcesqueue) $(INCLUDES)
$(objectstestqueue): $(sourcestestqueue)
$(CXX) -c $(sourcestestqueue) $(INCLUDES)
$(objectsheap): $(sourcesheap)
$(CXX) -c $(sourcesheap) $(INCLUDES)
$(objectstestheap): $(sourcestestheap)
$(CXX) -c $(sourcestestheap) $(INCLUDES)
$(objectsdijkstra): $(sourcesdijkstra)
$(CXX) -c $(sourcesdijkstra) $(INCLUDES)
$(objectstestdijkstra): $(sourcestestdijkstra)
$(CXX) -c $(sourcestestdijkstra) $(INCLUDES)
clean:
rm -f *.o
rm -f *.exe
testqueue: $(objectsqueue) $(objectstestqueue)
$(CXX) -o QueueTests.exe $(objectsqueue) $(objectstestqueue)
testheap: $(objectsheap) $(objectstestheap)
$(CXX) -o BinaryHeapTest.exe $(objectsheap) $(objectstestheap)
testdijkstra: $(objectsheap) $(objectsdijkstra) $(objectstestdijkstra)
$(CXX) -o DijkstraTest.exe $(objectsheap) $(objectsdijkstra) $(objectstestdijkstra)
To be able to debug an application, you need to compile it using the -g (debug) flag:
CXXFLAGS=-g
$(objectsqueue): $(sourcesqueue)
$(CXX) $(CXXFLAGS) -c $(sourcesqueue) $(INCLUDES)
...
testqueue: $(objectsqueue) $(objectstestqueue)
$(CXX) $(CXXFLAGS) -o QueueTests.exe $(objectsqueue) $(objectstestqueue)
....
you need to use this flag for all compilation rules.