i'm new to Makefile. I've to write a Makefile to build a shared libary.
CC =g++
CFLAGS =-fPIC -Wall -Wextra -c
LDFLAGS =-shared
RM =rm -rf
TARGET_LIB =lib/Automat.so
SRC_DIR =src/
LIB_DIR =lib/
DEP_DIR =dep/
SRCS=IFSM.h IState.h ITransition.h FSM.h State.h Transition.h Wildcard.h PrimeTransition.h SingleTransition.h Exception.h Type.h Error.h
OBJS=$(SRCS:.h=.o)
.PHONY: all
all: $(TARGET_LIB)
$(TARGET_LIB): $(SRC_DIR)$(OBJS)
$(CC) $(LDFLAGS) -o $# $^
$(SRC_DIR)$(SRCS:.h=.d):%.d:$(SRC_DIR)%.h
$(CC) $(CFLAGS) -MM $< > $(DEP_DIR)$#
include $(SRCS:.h=.d)
My problem is that i get the error
No rule to make target `IFSM.d'. Stop.
If i remove to file from SRCS the problem occurs with IState.d. All other .d files where builded correct (11 of 12).
All files exists and they are written correct (case-sensitiv).
I rly don't know where the error could be and i was searching for 2 hours now.
Any help would be great.
Best regards
Alex
You are including
$(SRCS:.h=.d)
that is, files called whatever.d in the local directory; but you have a rule to make
$(SRC_DIR)$(SRCS:.h=.d)
that is, files called src/whatever.d.
You need to decide where these files should live, and make both rules match.
Make sure that you are using tabs for indentation. Such mysterious failures are usually caused by using spaces, which are not supported by make.
Related
I have the following makefile that I use to build a program (a kernel, actually) that I'm working on. Its from scratch and I'm learning about the process, so its not perfect, but I think its powerful enough at this point for my level of experience writing makefiles.
AS = nasm
CC = gcc
LD = ld
TARGET = core
BUILD = build
SOURCES = source
INCLUDE = include
ASM = assembly
VPATH = $(SOURCES)
CFLAGS = -Wall -O -fstrength-reduce -fomit-frame-pointer -finline-functions \
-nostdinc -fno-builtin -I $(INCLUDE)
ASFLAGS = -f elf
#CFILES = core.c consoleio.c system.c
CFILES = $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
SFILES = assembly/start.asm
SOBJS = $(SFILES:.asm=.o)
COBJS = $(CFILES:.c=.o)
OBJS = $(SOBJS) $(COBJS)
build : $(TARGET).img
$(TARGET).img : $(TARGET).elf
c:/python26/python.exe concat.py stage1 stage2 pad.bin core.elf floppy.img
$(TARGET).elf : $(OBJS)
$(LD) -T link.ld -o $# $^
$(SOBJS) : $(SFILES)
$(AS) $(ASFLAGS) $< -o $#
%.o: %.c
#echo Compiling $<...
$(CC) $(CFLAGS) -c -o $# $<
#Clean Script - Should clear out all .o files everywhere and all that.
clean:
-del *.img
-del *.o
-del assembly\*.o
-del core.elf
My main issue with this makefile is that when I modify a header file that one or more C files include, the C files aren't rebuilt. I can fix this quite easily by having all of my header files be dependencies for all of my C files, but that would effectively cause a complete rebuild of the project any time I changed/added a header file, which would not be very graceful.
What I want is for only the C files that include the header file I change to be rebuilt, and for the entire project to be linked again. I can do the linking by causing all header files to be dependencies of the target, but I cannot figure out how to make the C files be invalidated when their included header files are newer.
I've heard that GCC has some commands to make this possible (so the makefile can somehow figure out which files need to be rebuilt) but I can't for the life of me find an actual implementation example to look at. Can someone post a solution that will enable this behavior in a makefile?
EDIT: I should clarify, I'm familiar with the concept of putting the individual targets in and having each target.o require the header files. That requires me to be editing the makefile every time I include a header file somewhere, which is a bit of a pain. I'm looking for a solution that can derive the header file dependencies on its own, which I'm fairly certain I've seen in other projects.
As already pointed out elsewhere on this site, see this page:
Auto-Dependency Generation
In short, gcc can automatically create .d dependency files for you, which are mini makefile fragments containing the dependencies of the .c file you compiled.
Every time you change the .c file and compile it, the .d file will be updated.
Besides adding the -M flag to gcc, you'll need to include the .d files in the makefile (like Chris wrote above).
There are some more complicated issues in the page which are solved using sed, but you can ignore them and do a "make clean" to clear away the .d files whenever make complains about not being able to build a header file that no longer exists.
You could add a 'make depend' command as others have stated but why not get gcc to create dependencies and compile at the same time:
DEPS := $(COBJS:.o=.d)
-include $(DEPS)
%.o: %.c
$(CC) -c $(CFLAGS) -MM -MF $(patsubst %.o,%.d,$#) -o $# $<
The '-MF' parameter specifies a file to store the dependencies in.
The dash at the start of '-include' tells Make to continue when the .d file doesn't exist (e.g. on first compilation).
Note there seems to be a bug in gcc regarding the -o option. If you set the object filename to say obj/_file__c.o then the generated _file_.d will still contain _file_.o, not obj/_file_c.o.
This is equivalent to Chris Dodd's answer, but uses a different naming convention (and coincidentally doesn't require the sed magic. Copied from a later duplicate.
If you are using a GNU compiler, the compiler can assemble a list of dependencies for you. Makefile fragment:
depend: .depend
.depend: $(SOURCES)
rm -f ./.depend
$(CC) $(CFLAGS) -MM $^>>./.depend;
include .depend
There is also the tool makedepend, but I never liked it as much as gcc -MM
You'll have to make individual targets for each C file, and then list the header file as a dependency. You can still use your generic targets, and just place the .h dependencies afterwards, like so:
%.o: %.c
#echo Compiling $<...
$(CC) $(CFLAGS) -c -o $# $<
foo.c: bar.h
# And so on...
Basically, you need to dynamically create the makefile rules to rebuild the object files when the header files change. If you use gcc and gnumake, this is fairly easy; just put something like:
$(OBJDIR)/%.d: %.c
$(CC) -MM -MG $(CPPFLAGS) $< | sed -e 's,^\([^:]*\)\.o[ ]*:,$(#D)/\1.o $(#D)/\1.d:,' >$#
ifneq ($(MAKECMDGOALS),clean)
include $(SRCS:%.c=$(OBJDIR)/%.d)
endif
in your makefile.
Over and above what #mipadi said, you can also explore the use of the '-M' option to generate a record of the dependencies. You might even generate those into a separate file (perhaps 'depend.mk') which you then include in the makefile. Or you can find a 'make depend' rule which edits the makefile with the correct dependencies (Google terms: "do not remove this line" and depend).
Simpler solution: Just use the Makefile to have the .c to .o compilation rule be dependent on the header file(s) and whatever else is relevant in your project as a dependency.
E.g., in the Makefile somewhere:
DEPENDENCIES=mydefs.h yourdefs.h Makefile GameOfThrones.S07E01.mkv
::: (your other Makefile statements like rules
::: for constructing executables or libraries)
# Compile any .c to the corresponding .o file:
%.o: %.c $(DEPENDENCIES)
$(CC) $(CFLAGS) -c -o $# $<
None of the answers worked for me. E.g. Martin Fido's answer suggests gcc can create dependency file, but when I tried that it was generating empty (zero bytes) object files for me without any warnings or errors. It might be a gcc bug. I am on
$ gcc --version gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-16)
So here's my complete Makefile that works for me; it's a combination of solutions + something that wasn't mentioned by anyone else (e.g. "suffix replacement rule" specified as .cc.o:):
CC = g++
CFLAGS = -Wall -g -std=c++0x
INCLUDES = -I./includes/
# LFLAGS = -L../lib
# LIBS = -lmylib -lm
# List of all source files
SRCS = main.cc cache.cc
# Object files defined from source files
OBJS = $(SRCS:.cc=.o)
# # define the executable file
MAIN = cache_test
#List of non-file based targets:
.PHONY: depend clean all
## .DEFAULT_GOAL := all
# List of dependencies defined from list of object files
DEPS := $(OBJS:.o=.d)
all: $(MAIN)
-include $(DEPS)
$(MAIN): $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
#suffix replacement rule for building .o's from .cc's
#build dependency files first, second line actually compiles into .o
.cc.o:
$(CC) $(CFLAGS) $(INCLUDES) -c -MM -MF $(patsubst %.o,%.d,$#) $<
$(CC) $(CFLAGS) $(INCLUDES) -c -o $# $<
clean:
$(RM) *.o *~ $(MAIN) *.d
Notice I used .cc .. The above Makefile is easy to adjust for .c files.
Also notice importance of these two lines :
$(CC) $(CFLAGS) $(INCLUDES) -c -MM -MF $(patsubst %.o,%.d,$#) $<
$(CC) $(CFLAGS) $(INCLUDES) -c -o $# $<
so gcc is called once to build a dependency file first, and then actually compiles a .cc file. And so on for each source file.
I believe the mkdep command is what you want. It actually scans .c files for #include lines and creates a dependency tree for them. I believe Automake/Autoconf projects use this by default.
I have a problem with building cpp files when I move them out of Makefile folder. Anyone knows why?
Snippet from the makefile:
CC = qcc -Vgcc_nto$(PLATFORM)
CXX = qcc -lang-c++ -Vgcc_nto$(PLATFORM)
LD = $(CXX)
DEPS = -Wp,-MMD,$(#:%.o=%.d),-MT,$#
CFLAGS=-Wall -g -ggdb -O0
DIR_SRC =./
DIR_OBJ =./
SRCS := $(wildcard $(DIR_SRC)/*.cpp)
OBJECTS := $(SRCS:$(DIR_SRC)/%.cpp=$(DIR_OBJ)/%.o)
all: hello_world_test
$(DIR_OBJ)/%.o : $(DIR_SRC)/%.c
$(CXX) $(CFLAGS) ${CPPFLAGS} ${DEPS} -c $< -o $#
hello_world_test: hello_world_test.o
$(CXX) hello_world_test.o $(LDFLAGS) $(LIBPATH) $(LDLIBS) -o $#
So in this way, everything is fine but when I move sources to one folder back called "test"
DIR_SRC =../test
it doesnt work anymore with the message:
make: *** No rule to make target 'hello_world_test.o', needed by 'hello_world_test'. Stop.
Because:
hello_world_test: hello_world_test.o
your hello_world_test depends on hello_world_test.o. But your rule tells make how to build $(DIR_OBJ)/%.o and hello_world_test.o doesn't match that pattern. Pattern matching in targets is simple string matching, it doesn't do pathname simplification. You should write your prerequisite as:
hello_world_test: $(DIR_OBJ)/hello_world_test.o
Note that you have two slashes here: one in DIR_OBJ and one after it. But anyway.
The reason it worked before is that make was using its built-in recipe to build object files, not your recipe; the built-in recipe has the pattern:
%.o : %.c
which matched your object file. If you run make with the -r option to remove all built-in rules, you would have seen a failure there as well.
Thank you for your answer. I found out that the problem was in the rule, like you said.
I changed to $(DIR_OBJ)/%.o : $(DIR_SRC)/%.cpp (before it was .c instead of .cpp :) ) and it works now with changing the DIR_SRC.
I didn't observe this since I was able to build from the current directory but realized after your answer about built-in rule.
Another questions:
1) Does this rule:
$(DIR_OBJ)/%.o : $(DIR_SRC)/%.cpp
$(CXX) $(CFLAGS) ${CPPFLAGS} ${DEPS} -c $< -o $#
says next: do compile all .cpp files and make .o files out of it and put the .o files in DIR_OBJ?
2) Why I cant change DIR_OBJ location to for instance:
DIR_OBJ =../test and then use hello_world_test: $(DIR_OBJ)/hello_world_test.o to build the executable?
When I do it I get an error: cannot find hello_world_test.o: No such file or directory.
I see that .o and .d files are created in the directory where DIR_OBJ is defined (either in ./ or in ../test) and then it makes me quite confused why hello_world_test cant fine prerequisite $(DIR_OBJ)/hello_world_test.o but it only looks in the current folder where the Makefile is.
I realized what was the problem:
I haven't added $(DIR_OBJ)/hello_world_test.o in
$(CXX) hello_world_test.o $(LDFLAGS) $(LIBPATH) $(LDLIBS) -o $#
but now still confused, if my understanding is right that $(DIR_OBJ)/%.o : $(DIR_SRC)/%.cpp will create $(DIR_OBJ)/hello_world_test.o how come that hello_world_client: $(DIR_OBJ)/hello_world_client.o couldn't find prerequisite?
I have the following Makefile in a directory full of .cpp and .h files:
CFLAGS=-g -std=c++0x -Wall -pedantic -Wextra -D __STDC_LIMIT_MACROS -D __STDC_FORMAT_MACROS -O0
CXX=g++
LDFLAGS=-lgmp -lmathsat -lz3
all: Foo.o Bar.o
$(CXX) $(CFLAGS) -o myexe Foo.o Bar.o $(LDFLAGS)
depend: .depend
.depend: $(wildcard *.cpp)
rm -f ./.depend
$(CXX) $(CFLAGS) -MM $^ > ./.depend
include .depend
%.o: %.cpp
$(CXX) $(CFLAGS) $(INCLUDE) $< -c
clean:
rm -f *.o myexe
When I hit make, it invariably executes the last step (linking) even when none of the .o files have changed. How can I prevent make from doing that? I'd expect make to output Everything up-to-date or something similar.
I'm on a i686 GNU/Linux machine with GNU Make 3.82 and g++ version 4.8.2.
Make relinks your project because it tries to build all. The rule for all does not create any file named all. Instead it produces myexe. Next time you run make, it will see that there's no all, but there's a rule to build one, so it dutifully executes that rule which happens to link myexe every time you run make.
In order to fix your problem you need to change your makefile to look roughly like this:
all: myexe
echo Build done
myexe: <myexe dependencies go here>
$(CXX) $(CFLAGS) -o myexe $(wildcard *.o) $(LDFLAGS)
Make always tries to build the top rule. For you, this is all. Since your all rule doesn't actually make an all file it will always be run.
Your probably want your all rule to be a myexe rule and, if you want an explicit all rule, have a dependency only rule: all: myexe.
(With GNU Make, you might want to explicitly declare those targets which aren't supposed to generate a real file with a .PHONY rule. e.g. .PHONY: all depend clean.)
make is a rule-based expert system.
You give it a heap of rules and a target (default target is the first one listed), and then it builds a complete dependency tree.
All parts are rebuilt iff they are non-existent resp. older than their dependencies, recursively.
The rule you are stumbling over is this: Because the target all does not create an output file all, make invokes the non-existent-or-outdated rule.
You can correct this by making the target all not do any work but instead just depend on the output file. Marking it .PHONY is also a good idea.
I am now studying C++. I want a makefile which will compile all of the cpp files in the current directory to separate executables. For example:
In a directory there are 3 c++ files, such as examp1.cpp, examp2.cpp and examp3.cpp. I want a makefile which will compile and link them and give examp1.exe, examp2.exe and examp3.exe
I have created a bash script to compile all of them and create exes but I think; that's not the exact way to do this.
I have a a Makefile for ".c", but that does not seem to work here. It is only creating object files and not actually linking it. It is as follows:
SRCS=$(wildcard *.c)
OBJS=(SRCS:.c=.o)
all: $(OBJS)
The above code compiles all the new and modified ".c" files to ".o" files with same name in the current directory.
The bash script I am using to create executables is as follows:
for i in ./*.cpp
do
g++ -Wno-deprecated $i -o `basename $i .cpp`".exe"
done
This means I want whatever ".cpp" files I put in that directory, by using a simple "make all" or anything like that it should compile.
A minimal Makefile that does what you want would be:
#Tell make to make one .out file for each .cpp file found in the current directory
all: $(patsubst %.cpp, %.out, $(wildcard *.cpp))
#Rule how to create arbitary .out files.
#First state what is needed for them e.g. additional headers, .cpp files in an include folder...
#Then the command to create the .out file, probably you want to add further options to the g++ call.
%.out: %.cpp Makefile
g++ $< -o $# -std=c++0x
You'll have to replace g++ by the compiler you're using and possibly adjust some platform specific setting, but the Makefile itself should work.
This is the Makefile that I use
CC = gcc
CFLAGS = -g -O2 -std=gnu99 -static -Wall -Wextra -Isrc -rdynamic -fomit-frame-pointer
all: $(patsubst %.c, %.out, $(wildcard *.c))
%.out: %.c Makefile
$(CC) $(CFLAGS) $< -o $# -lm
clean:
rm *.out
You should paste it somewhere in your home and whenever you change the dirctory just copy it there. I use an alias in my ~/.basrc to copy it
alias get_makefile_here='cp ~/Makefile ./'
Simply press make and bam, you're done. Also notice the fact that once you're done with the old files it will not rebuild their executable.
My answer builds on top of the answer by #Haatschii
I don't prefer to have the .out prefix to my binaries. Also I used his existing Make syntax to perform clean as well.
CXX=clang++
CXXFLAGS=-Wall -Werror -std=c++11
all: $(patsubst %.cpp, %.out, $(wildcard *.cpp))
%.out: %.cpp Makefile
$(CXX) $(CXXFLAGS) $< -o $(#:.out=)
clean: $(patsubst %.cpp, %.clean, $(wildcard *.cpp))
%.clean:
rm -f $(#:.clean=)
The simplest makefile you can create that might work for you is this:
all: examp1.exe examp2.exe examp3.exe
That will use make's default rules to create your three programs.
I want a build rule to be triggered by an include directive if the target of the include is out of date or doesn't exist.
Currently the makefile looks like this:
program_NAME := wget++
program_H_SRCS := $(wildcard *.h)
program_CXX_SRCS := $(wildcard *.cpp)
program_CXX_OBJS := ${program_CXX_SRCS:.cpp=.o}
program_OBJS := $(program_CXX_OBJS)
DEPS = make.deps
.PHONY: all clean distclean
all: $(program_NAME) $(DEPS)
$(program_NAME): $(program_OBJS)
$(LINK.cc) $(program_OBJS) -o $(program_NAME)
clean:
#- $(RM) $(program_NAME)
#- $(RM) $(program_OBJS)
#- $(RM) make.deps
distclean: clean
make.deps: $(program_CXX_SRCS) $(program_H_SRCS)
$(CXX) $(CPPFLAGS) -MM $(program_CXX_SRCS) > make.deps
include $(DEPS)
The problem is that it seems like the include directive is executing before the rule to build make.deps which effectively means that make is either getting no dependency list if make.deps doesn't exist or always getting the make.deps from the previous build and not the current one.
For example:
$ make clean
$ make
makefile:32: make.deps: No such file or directory
g++ -MM addrCache.cpp connCache.cpp httpClient.cpp wget++.cpp > make.deps
g++ -c -o addrCache.o addrCache.cpp
g++ -c -o connCache.o connCache.cpp
g++ -c -o httpClient.o httpClient.cpp
g++ -c -o wget++.o wget++.cpp
g++ addrCache.o connCache.o httpClient.o wget++.o -o wget++
Edit
I read the docs for the include directive, and it sounds like if the include target doesn't exist it will continue processing the parent makefile try and build the target, but it's not completely clear to me how this works:
If an included makefile cannot be
found in any of these directories, a
warning message is generated, but it
is not an immediately fatal error;
processing of the makefile containing
the include continues. Once it has
finished reading makefiles, make will
try to remake any that are out of date
or don't exist. See section How
Makefiles Are Remade. Only after it
has tried to find a way to remake a
makefile and failed, will make
diagnose the missing makefile as a
fatal error.
ANSWER
This is a modification of the answer I accepted. The one thing missing was that the dependency files also depend on the sources, and won't get regenerated unless they are added to the deps files which are being included:
%.d: $(program_CXX_SRCS)
# $(CXX) $(CPPFLAGS) -MM $*.cpp | sed -e 's#^\(.*\)\.o:#\1.d \1.o:#' > $#
sed adds the name of the .d file to the beginning of each dependency line like so:
foo.d foo.o: foo.cpp foo.h bar.h baz.h
I got the idea from this amazing paper on the dangers of recursive make:
Recursive Make Considered Harmful
I also add the following to the makefile:
clean_list += ${program_SRCS:.c=.d}
# At the end of the makefile
# Include the list of dependancies generated for each object file
# unless make was called with target clean
ifneq "$(MAKECMDGOALS)" "clean"
-include ${program_SRCS:.c=.d}
endif
You are relying on an implicit rule to compile your .cpp files. You have to redefine it to use the -MM and -MF flags that will create the dependency file.
%.o: %.cpp
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c $< -o $# -MM -MF $#.d
Then, you have to include these dependencies files in the Makefile, using -include that will not error when the dependencies files do not exist yet (on the first time, or after a clean).
program_DEPS := $(program_OBJS:.o=.o.d)
-include $(program_DEPS)
And remember to add the rm command for the dependencies files in the clean rule.
An important point that it took me a while to grasp is that the make.deps from the previous build are good enough. Think about it: for a given object file, the only way the list of dependency files can change is if... one of the old dependency files has been altered. And if that's the case, then the old make.deps will cause that object file to be rebuilt, and if rebuilding the object file also rebuilds make.deps, then everything will be up to date. You don't have to rebuild make.deps before checking to see which objects must be rebuilt.
The include directives work like they do in C and C++ - they are processed before anything else happens, to build the "real" makefile that make then processes. Specifically, they are processed before any rules are fired.