Makefile for compiling different "modules" which can include each other - c++

Question

We have a project with a module structure like this:
- Project
- mod1
- mod1.cpp
- mod1.h
- main.cpp
- mod2
- mod2.cpp
- mod2.h
- main.cpp
- more modules
The main.cpp file in each module instantiates and tests that module. One module can include and use another module. So for example, module 1 can include module 2 and eventually other modules.
We want to create a makefile which compiles and includes the correct modules and main.cpp file. So if I write "make module2" the makefile would compile mod2.cpp, main.cpp (in module 2) and include mod2.h. If I write "make module1" the makefile would compile mod2.cpp, mod1.cpp main.cpp (in module 1) and include mod1.h and mod2.h.
My experience with makefiles is modest, and I've used several days on this without success.
Making it generic would be preferable so that adding a new module would not require major changes to the makefile.
The closest solution I got is this:
.PHONY: clean
FLAGS=-std=c++11 -g -I"$(SYSTEMC_PATH)/include" -I"$(SYSTEMC_PATH)" -L"$(SYSTEMC_PATH)/lib-linux64" -lsystemc $(addprefix -I, $(wildcard src/*))
SRCS_WITHOUT_MAIN= $(filter-out %main.cpp, $(shell find src -name '*.cpp'))
TARGET_OBJS=$(subst src, .build/obj, $(subst .cpp,.o,$(SRCS_WITHOUT_MAIN)))
all: $(filter-out unit_test, $(subst src/, ,$(wildcard src/*)))
.SECONDARY:
.build/obj/%.o: src/%.cpp
#mkdir -p $(shell dirname $#)
g++ $(FLAGS) $^ -c -o $#
clean:
#rm -r .build
%: $(TARGET_OBJS) .build/obj/%/main.o
#mkdir -p $(shell dirname .build/bin/$#)
g++ $(FLAGS) $^ -o .build/bin/$#
SRCS_WITHOUT_MAIN holds all the cpp files of all modules except the main files. TARGET_OBJS are the corresponding list of object files. The % target matches on, for example "mod1" which compiles all cpp files and main.cpp of mod1.
The problem is, occasionally we get segfaults while running after compiling, and we need to do a "make clean && make" for it to work again. One day I used 4 hours debugging my code just to find out the makefile is some kind of broken. Now everybody on the project uses "make clean && make" all the time in fear of going through the same as I did...
Does anyone know a clever way to do this? By the way: this is a SystemC project.

Answer 1

Here is a crude but effective makefile that will do the job:
CC=g++
vpath %.h mod1 mod2
module1: mod1.o mod2.o main1.o
$(CC) $^ -o $#
module2: mod2.o main2.o
$(CC) $^ -o $#
mod1.o: mod1/mod1.cpp mod1.h mod2.h
mod2.o: mod2/mod2.cpp mod1.h mod2.h
main1.o: mod1/main.cpp mod1.h mod2.h
main2.o: mod2/main.cpp mod1.h mod2.h
%.o:
$(CC) -c $< -o $#
Note:
It puts all object files (e.g. mod1.o) in the parent directory, which is where I presume the makefile is.
It names the two "main" object files "main1.o" and "main2.o". Having two files with the same name in the same codebase is just asking for trouble.
Further refinements are possible; this is designed for simplicity.

Answer 2

The strategy of using pattern rules to match names of modules which can depend upon each other may not be possible using GNU make. From the GNU make 3.82 manual (edition 0.71)
No single implicit rule can appear more than once in a chain. This
means that 'make' will not even consider such a ridiculous thing as
making 'foo' from 'foo.o.o' by running the linker twice. This
constraint has the added benefit of preventing any infinite loop in
the search for an implicit rule chain.
(I found some discussion of this here - things may be different in later versions.)
So if module3 depends on module2, and module2 depends on module1, if we run a pattern rule to build module3, we can't then use the same rule to build module2.
It is possible to get round this using static pattern rules, where the list of targets the rule is matched is specified. I've edited my answer to use these.
You could adapt the following to your problem. Each subdirectory has a number of "*.in" files, and when the subdirectory is built files with the corresponding "*.out" file is created. The modules themselves depend on each other: in this case, mod3 depends on mod2, which in turn depends on mod1. When e.g. the file "mod1/file.in" is updated, running "make mod3" causes mod1, mod2 and mod3 to be rebuilt.
MODULES=mod1 mod2 mod3
mod1_DEPS =
mod2_DEPS = mod1
mod3_DEPS = mod2
TARGET_OBJS=$(subst .in,.out,$(shell find $# -name '*.in'))
.PRECIOUS: %.out
%.out: %.in
touch $#
%.in:
.SECONDEXPANSION:
$(MODULES) : $$(TARGET_OBJS) $$($$#_DEPS)
#echo Building module $#
The .SECONDEXPANSION target and using $$ instead of $ allows access to the $# variable in the TARGET_OBJS macro.
To treat modules differently whether they are being built as programs or libraries, you could have two separate rules, which search for their sources differently:
MODULES=mod1 mod2 mod3
mod1_DEPS =
mod2_DEPS = mod1_AS_MODULE
mod3_DEPS = mod2_AS_MODULE
TARGET_OBJS=$(subst .in,.out,$(shell find $* -name '*.in'))
MODULE_TARGET_OBJS= $(filter-out main.out $(subst .in,.out,$(shell find $* -name '*.in')))
# (elided code as above example)
$(addsuffix _AS_MODULE, $(MODULES)) : %_AS_MODULE: $$(MODULE_TARGET_OBJS) $$(%_DEPS)
#echo Building module $#
$(addsuffix _AS_PROGRAM, $(MODULES)) : %_AS_PROGRAM: $$(TARGET_OBJS) $$(%_DEPS)
#echo Building program $#
This would be invoked as, say, "make mod3_AS_PROGRAM".