Some questions on Makefile - c++

Question

I am trying to understand a second level makefile of uboot (this makefile was in a sub directory)
a) What is the difference between $(COBJS:.o=.c) and COBJS := test_main.o
b) What is the meaning of $(call cmd_link_o_target, $(OBJS)). What is the cmd_link_o_target and what is the call statement doing
c) Does this line creating 2 targets ?
ALL := $(obj).depend $(LIB)
===================================Makefile===================
include $(TOPDIR)/config.mk
LIB = $(obj)libtest.o
SOBJS := test.o
COBJS := test_main.o
COBJS += diagnostic.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
ALL := $(obj).depend $(LIB)
all: $(ALL)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

Answer 1

a) $(COBJS:.o=.c) performs a suffix substitution on every element of COBJ which in this case is equivalent to using SRCS := test.S test_main.c
b) $(call cmd_link_o_target, $(OBJS)) is a way to create a parametric function in make. It will take the expression for cmd_link_o_target (contained in the included file) and replace every occurence of $(1) with $(OBJS) further expanded.
c) yes, it does (obj is also contained in the file included by the Makefile).
In case you are wondering, the difference between = and := assignments is that = allows for recursive replacement, while := is static, i.e. expanded only once, without creating references to other variables.