I am currently trying to build Face Tracker (by Jason Saragih) with "make" in my Windows 7 x64, but all I'm getting is: "No rule to make target src/lib/IO.o, needed by bin/face_tracker".
Does anyone have any idea of what is happening, please?
This is the makefile (also available in Jason Saragih's page):
# Paths
OPENCV_PATH=/OpenCV246/
# Programs
CC=
CXX=g++
# Flags
ARCH_FLAGS=-arch x86_64
CFLAGS=-Wextra -Wall -pedantic-errors $(ARCH_FLAGS) -O3
LDFLAGS=$(ARCH_FLAGS)
DEFINES=
INCLUDES=-I$(OPENCV_PATH)/include -Iinclude/
LIBRARIES=-L$(OPENCV_PATH)/lib -lopencv_core -lopencv_highgui -lopencv_imgproc -lopencv_objdetect
# Files which require compiling
SOURCE_FILES=\
src/lib/IO.cc\
src/lib/PDM.cc\
src/lib/Patch.cc\
src/lib/CLM.cc\
src/lib/FDet.cc\
src/lib/PAW.cc\
src/lib/FCheck.cc\
src/lib/Tracker.cc
# Source files which contain a int main(..) function
SOURCE_FILES_WITH_MAIN=src/exe/face_tracker.cc
# End Configuration
SOURCE_OBJECTS=$(patsubst %.cc,%.o,$(SOURCE_FILES))
ALL_OBJECTS=\
$(SOURCE_OBJECTS) \
$(patsubst %.cc,%.o,$(SOURCE_FILES_WITH_MAIN))
DEPENDENCY_FILES=\
$(patsubst %.o,%.d,$(ALL_OBJECTS))
all: bin/face_tracker
%.o: %.cc Makefile
## Make dependecy file
$(CXX) -MM -MT $# -MF $(patsubst %.cc,%.d,$<) $(CFLAGS) $(DEFINES) $(INCLUDES) $<
## Compile
$(CXX) $(CFLAGS) $(DEFINES) $(INCLUDES) -c -o $# $<
-include $(DEPENDENCY_FILES)
bin/face_tracker: $(ALL_OBJECTS)
$(CXX) $(LDFLAGS) $(LIBRARIES) -o $# $(ALL_OBJECTS)
.PHONY: clean
clean:
#echo "Cleaning"
#for pattern in '*~' '*.o' '*.d' ; do \
find . -name "$$pattern" | xargs rm ; \
done
Thanks,
Fabio
Related
I would like to add a cpp file to use the c functions. I made the file but the problem becomes how to include the file in the makefile.All I know is that I should compile with c++ after C. and then link it together.
May someone point me in the right direction.
This is a snippet of testcpp.cpp
extern "C" {
#include "darknet.h"
}
Below is the makefile but i keep getting No rule to make target 'obj/test.cpp', needed by 'darknet'.
GPU=0
CUDNN=0
OPENCV=0
NNPACK=1
NNPACK_FAST=1
ARM_NEON=1
OPENMP=0
DEBUG=0
QPU_GEMM=1
ARCH= -gencode arch=compute_30,code=sm_30 \
-gencode arch=compute_35,code=sm_35 \
-gencode arch=compute_50,code=[sm_50,compute_50] \
-gencode arch=compute_52,code=[sm_52,compute_52]
# -gencode arch=compute_20,code=[sm_20,sm_21] \ This one is deprecated?
# This is what I use, uncomment if you know your arch and want to specify
# ARCH= -gencode arch=compute_52,code=compute_52
VPATH=./src/:./examples
SLIB=libdarknet.so
ALIB=libdarknet.a
EXEC=darknet
OBJDIR=./obj/
CC=gcc
NVCC=nvcc
AR=ar
ARFLAGS=rcs
OPTS=-Ofast
LDFLAGS= -lm -pthread
COMMON= -Iinclude/ -Isrc/
#CFLAGS=-Wall -Wno-unknown-pragmas -Wfatal-errors -fPIC
#CFLAGS=-Wall -Wno-unknown-pragmas -Wfatal-errors -fPIC -march=native -mfpmath=sse
CFLAGS=-Wall -Wno-unknown-pragmas -Wfatal-errors -fPIC -mcpu=cortex-a53
ifeq ($(OPENMP), 1)
CFLAGS+= -fopenmp
endif
ifeq ($(DEBUG), 1)
OPTS=-O0 -g
endif
CFLAGS+=$(OPTS)
ifeq ($(OPENCV), 1)
COMMON+= -DOPENCV
CFLAGS+= -DOPENCV
LDFLAGS+= `pkg-config --libs opencv`
COMMON+= `pkg-config --cflags opencv`
endif
ifeq ($(GPU), 1)
COMMON+= -DGPU -I/usr/local/cuda/include/
CFLAGS+= -DGPU
LDFLAGS+= -L/usr/local/cuda/lib64 -lcuda -lcudart -lcublas -lcurand
endif
ifeq ($(CUDNN), 1)
COMMON+= -DCUDNN
CFLAGS+= -DCUDNN
LDFLAGS+= -lcudnn
endif
ifeq ($(QPU_GEMM), 1)
COMMON+= -DQPU_GEMM
CFLAGS+= -DQPU_GEMM
LDFLAGS+= -lqmkl
endif
ifeq ($(NNPACK), 1)
COMMON+= -DNNPACK
CFLAGS+= -DNNPACK
LDFLAGS+= -lnnpack -lpthreadpool
endif
ifeq ($(NNPACK_FAST), 1)
COMMON+= -DNNPACK_FAST
CFLAGS+= -DNNPACK_FAST
endif
ifeq ($(ARM_NEON), 1)
COMMON+= -DARM_NEON
CFLAGS+= -DARM_NEON -mfpu=neon-vfpv4 -funsafe-math-optimizations -ftree-vectorize
endif
OBJ=gemm.o utils.o cuda.o deconvolutional_layer.o convolutional_layer.o list.o image.o activations.o im2col.o col2im.o blas.o crop_layer.o dropout_layer.o maxpool_layer.o softmax_layer.o data.o matrix.o network.o connected_layer.o cost_layer.o parser.o option_list.o detection_layer.o route_layer.o box.o normalization_layer.o avgpool_layer.o layer.o local_layer.o shortcut_layer.o activation_layer.o rnn_layer.o gru_layer.o crnn_layer.o demo.o batchnorm_layer.o region_layer.o reorg_layer.o tree.o lstm_layer.o
EXECOBJA=captcha.o lsd.o super.o art.o tag.o cifar.o go.o rnn.o segmenter.o regressor.o classifier.o coco.o yolo.o detector.o nightmare.o attention.o darknet.o
EXECOBJA1=testcpp.cpp
ifeq ($(GPU), 1)
LDFLAGS+= -lstdc++
OBJ+=convolutional_kernels.o deconvolutional_kernels.o activation_kernels.o im2col_kernels.o col2im_kernels.o blas_kernels.o crop_layer_kernels.o dropout_layer_kernels.o maxpool_layer_kernels.o avgpool_layer_kernels.o
endif
EXECOBJ = $(addprefix $(OBJDIR), $(EXECOBJA))
EXECOBJ1 = $(addprefix $(OBJDIR), $(EXECOBJA1))
OBJS = $(addprefix $(OBJDIR), $(OBJ))
DEPS = $(wildcard src/*.h) Makefile include/darknet.h
CPP=g++
#all: obj backup results $(SLIB) $(ALIB) $(EXEC)
all: obj results $(SLIB) $(ALIB) $(EXEC)
$(EXEC): $(EXECOBJ) $(ALIB)
$(CC) $(COMMON) $(CFLAGS) $^ -o $# $(LDFLAGS) $(ALIB)
$(EXEC): $(EXECOBJ1)
$(CPP) -Wall $^ -o $# $(LDFLAGS)
$(ALIB): $(OBJS)
$(AR) $(ARFLAGS) $# $^
$(SLIB): $(OBJS)
$(CPP) $(CFLAGS) -shared $^ -o $#
$(OBJDIR)%.o: %.c $(DEPS)
$(CC) $(COMMON) $(CFLAGS) -c $< -o $#
$(OBJDIR)%.o: %.cu $(DEPS)
$(NVCC) $(ARCH) $(COMMON) --compiler-options "$(CFLAGS)" -c $< -o $#
obj:
mkdir -p obj
backup:
mkdir -p backup
results:
mkdir -p results
.PHONY: clean
clean:
rm -rf $(OBJS) $(SLIB) $(ALIB) $(EXEC) $(EXECOBJ)
I thought
$(EXEC): $(EXECOBJ1)
$(CPP) -Wall $^ -o $# $(LDFLAGS)
would compile the cpp file and
$(OBJDIR)%.o: %.c $(DEPS)
$(CC) $(COMMON) $(CFLAGS) -c $< -o $#
would link it
I think you need a recipe to compile object files from .cpp file:
$(OBJDIR)%.o: %.cpp $(DEPS)
$(CXX) $(COMMON) $(CFLAGS) -c $< -o $#
The error you describe probably comes from an incorrect usage of vpath: I don't think its usage is necessary here.
But basically I agree with #Basile Starynkevitch : you might be better rewriting from scratch. I have a few suggestions:
1 - Clearly separate in different folders programs (C or C++ files that hold a main() function) and library files (C or C++ files that hold functions). This will be useful for linking.
For example:
|
+--lib // holds "library" code
+--app // holds programs
+--headers
+--BUILD
|
+-- obj
| |
| +-- app
| +-- lib
|
+-- bin
2 - Automatically generate both object files and programs from source files:
SRC_FILES_LIB = $(wildcard lib/*.cpp)
SRC_FILES_APP = $(wildcard app/*.cpp)
OBJ_FILES_LIB = $(patsubst lib/%.cpp,BUILD/obj/lib/%.o,$(SRC_FILES_LIB))
OBJ_FILES_APP = $(patsubst app/%.cpp,BUILD/obj/app/%.o,$(SRC_FILES_APP))
EXEC_FILES = $(patsubst app/%.cpp,BUILD/bin/%,$(SRC_FILES_APP))
3 - add a target that builds the programs:
all: $(EXEC_FILES)
#echo "done"
After that, its just a matter of providing the sufficient pattern rule.
(sorry, no more time for that)
1. My file structure is:
build/
include/
-Sort.h
src/
-Sort.cpp
-main.cpp
2. My Makefile:
C++ = g++
SRCPATH := ./src
BUILDPATH := ./build
SORTINCPATH := ./include
TARGET := $(BUILDPATH)/sort
CPPFLAGS := -c -g -Wall -O0
INCPATH := -I./ -I$(SORTINCPATH)
CPPFILES += $(wildcard $(SRCPATH)/*.cpp)
CFILES += $(wildcard $(SRCPATH)/*.c)
HEADFILES += $(wildcard $(SORTINCPATH)/*.h)
CPPOBJS += $(CPPFILES:.cpp=.o)
COBJS += $(CFILES:.c=.o)
.PHONY : all
all: $(TARGET)
$(TARGET): $(CPPOBJS) $(COBJS)
$(C++) $(CPPFLAGS) -o $# $(CPPOBJS) $(COBJS)
%.o : %.c $(HEADFILES)
$(C++) $(CPPFLAGS) $(INCPATH) $< -o $#
%.O : %.cpp $(HEADFILES)
$(C++) $(CPPFLAGS) $(INCPATH) $< -o $#
.PHONY : clean
clean:
-rm $(TARGET) $(COBJS) $(CPPOBJS)
3. Sort.h
sort.h
4. Sort.cpp
sort-1.cpp
sort-2.cpp
5. When I run make, it shows the following:
g++ -c -g -Wall -O0 -c -o src/Sort.o src/Sort.cpp
and says "src/Sort.cpp:3:18: fatal error: Sort.h: no such file or directory".
I hope you can help me find out where the problem is.
Thank you so much!
I have the following make file:
.SECONDEXPANSION:
CXX = g++
CXXFLAGS = -Wall -W -ansi -I. -I../Include
BUILD_DIR = obj
OUT = bin/EngineTests
SRC = LiveTestReporterStdout.cpp \
EngineTests.cpp \
IntegratorValidationTest.cpp \
PRIVATE_SRC = Private/Unit/BlockTests/AlertBlockTest.cpp \
Private/Unit/BlockTests/CapBlockTest.cpp \
Private/TestHelpers.cpp
OBJS = $(patsubst %.cpp, $(BUILD_DIR)/%.o, $(SRC))
all: $(OUT)
private: SRC += $(PRIVATE_SRC)
private: $(OUT)
$(BUILD_DIR)/%.o : %.cpp
#echo $(CXX) $(CXXFLAGS) $<
#mkdir -p $(dir $#)
#$(CXX) $(CXXFLAGS) -c $< -o $#
$(OUT): $(OBJS)
#echo Linking $# ...
# blah
The goal being able to do make to build all from just $(SRC) and make private to build from $(SRC) + $(PRIVATE_SRC). But it doesnt work - I'm aware that target specific variables cant be used for pre-reqs and the solution somehow involves secondary expansion, but cant get it to work.
I have tried OBJS = $$(patsubst %.cpp, $(BUILD_DIR)/%.o, $$(SRC)) and various things like that.
Many thanks
I am trying to build excutables for multiple files which are built in the same way. When i run make all the excutables should be generated. I am getting error at prerequisites part of the macro.
CXX = g++
CXX_FLAGS = -g -Wall
LD_FLAGS =
INC_DIR = -I/my/path/include
SRC_DIR = .
LIB_DIR = -L$/my/path/lib
OBJ_DIR = obj
EXE_DIR = exe
SRCS := $(foreach s_dir, $(SRC_DIR), $(wildcard $(s_dir)/*.cpp))
OBJS := $(patsubst $(SRC_DIR)/%.cpp, $(OBJ_DIR)/%.o, $(SRCS))
EXES := $(patsubst $(SRC_DIR)/%.cpp, $(EXE_DIR)/%.out, $(SRCS))
all: create_directories create_objects create_exes
create_directories:
#echo "Creating $(OBJ_DIR) and $(EXE_DIR)..."
#mkdir -p obj
#mkdir -p exe
create_objects:
$(foreach b_dir, $(OBJ_DIR), $(eval $(call build-objects, $(b_dir))))
create_exes:
$(foreach ot, $(EXE_DIR), $(eval $(call build-exes, $(ot))))
define build-objects
$1/%.o: %.cpp
$(CXX) $(CXX_FLAGS) $(INC_DIR) -MMD -MP -c $$< -o $$#
endef
define build-exes
$1/%.out:obj/%.o
$(CXX) $(LD_FLAGS) -o $# $(OBJS) $(LIB_DIR) -lmylib
endef
Is this a right way to do generate multiple exes or any other simple way?
If I'm reading this makefile right, then it's much too complicated.
First let's have a rule to build object files:
$(OBJ_DIR)/%.o: %.cpp
$(CXX) $(CXX_FLAGS) $(INC_DIR) -MMD -MP -c $< -o $#
Now if we're not sure about the existence of obj/, we could add a rule to create it, but for the moment let's just put in a failsafe (we'll come back to this later):
$(OBJ_DIR)/%.o: %.cpp
#mkdir -p $(OBJ_DIR)
$(CXX) $(CXX_FLAGS) $(INC_DIR) -MMD -MP -c $< -o $#
And a similar rule to build the executables:
$(EXE_DIR)/%.out: $(OBJ_DIR)/%.o
#mkdir -p $(EXE_DIR)
$(CXX) $(LD_FLAGS) -o $# $^ $(LIB_DIR) -lmylib
And finally (at the top) some variables, the lists of files, and the all rule:
CXX = g++
CXX_FLAGS = -g -Wall
LD_FLAGS =
INC_DIR = -I/my/path/include
SRC_DIR = .
LIB_DIR = -L$/my/path/lib
OBJ_DIR = obj
EXE_DIR = exe
SRCS := $(wildcard $(SRC_DIR)/*.cpp)
EXES := $(patsubst $(SRC_DIR)/%.cpp, $(EXE_DIR)/%.out, $(SRCS))
# Let the object files take care of themselves
all: $(EXES)
That's all you need. Once this is working perfectly, we can discuss refinements like rules for building directories.
How do I use different compiler flags for different source files in a Makefile? For example, I'd like a Makefile that will produce:
g++ -c -COMPILER_FLAGS_1 -g source1.cpp -o source1.o
g++ -c -COMPILER_FLAGS_2 -g source2.cpp -o source2.o
g++ -c -COMPILER_FLAGS_2 -g source3.cpp -o source3.o
g++ -c -COMPILER_FLAGS_2 -g source4.cpp -o source4.o
g++ -c -COMPILER_FLAGS_3 -g source5.cpp -o source5.o
g++ -c -COMPILER_FLAGS_3 -g source6.cpp -o source6.o
g++ -c -COMPILER_FLAGS_3 -g source7.cpp -o source7.o
g++ -g -o output source1.o source2.o source3.o source4.o source5.o source6.o source7.o
At the moment I've got about 20 source files (and that's expected to grow), so an easy to maintain file would be nice.
Thanks in advance.
You could do something like the following (untested, so the syntax might be slightly off):
OBJS_1 := source1.o
OBJS_2 := source2.o source3.o source4.o
OBJS_3 := source5.o source6.o source7.o
OBJS := $(OBJS_1) $(OBJS_2) $(OBJS_3)
output: $(OBJS)
$(CXX) -g -o $# $^
$(OBJS_1): CXXFLAGS := $(COMPILER_FLAGS_1)
$(OBJS_2): CXXFLAGS := $(COMPILER_FLAGS_2)
$(OBJS_3): CXXFLAGS := $(COMPILER_FLAGS_3)
$(OBJS): %.o: %.cpp
$(CXX) -c $(CXXFLAGS) -g $< -o $#
Here is UNIX/LINUX makefile which I wrote and tested on Solaris LINUX to handle different compilation flags for different sections of a GNUmakefile. Please let me know if it can be improved. Thank you
# GNUmakefile
#
# makefile for mdRightFielder
#
# Builds:
# libmdRightFielder.so or libmdRightFielder.sl
ifndef SUB
include ../header.mk
else
VPATH=../Source:../Source/PCRE:../Source/SQLite:../../cpswindows/Source:../../util/mdLicense
INCL=-I../Include -I../Include/PCRE -I../Include/SQLite -I../../cpswindows/Include -I ../../util -I../../util/mdLicense
APIOBJ=cGlobalDataDestructor.o cPCRE.o CppInterface.o cRightFielder-FillTokenGaps.o
PCREOBJ=pcre_chartables.o pcre_compile.o pcre_exec.o pcre_fullinfo.o pcre_get.o pcre_globals.o pcre_newline.o \
pcre_tables.o pcre_try_flipped.o
SQLITEOBJ=sqlite3.o
CPSWINDOWSOBJ=BinarySearch.o cConfigFile.o cCriticalSection.o cDateTime.o cException.o cFile.o cSQLite.o \
QuickSort.o StringFunctions.o
MDLICENSEOBJ=CBigNum.o mdLicense.o RSA.o
ifeq ($(CPU),sparc)
ifdef workshop
CALIGN=-xmemalign=1s
ifdef release
CXXALIGN=-Qoption cg -xmemalign=1s
else
CXXALIGN=-Qoption ccfe -y-xmemalign=1s
endif
endif
endif
COMPILER_FLAGS_1=-D_NO_GUI
COMPILER_FLAGS_2=-D_NO_GUI -DHAVE_CONFIG_H
CXXFLAGS+=-DPCRE_STATIC -DUSE_STATIC
CFLAGS+=-D_NO_GUI -DHAVE_CONFIG_H -DPCRE_STATIC -DUSE_STATIC
DEPFLAGS+=-DLINK_SIZE=2 -D_NO_GUI -DHAVE_CONFIG_H -DPCRE_STATIC -DUSE_STATIC
.PHONY: all clean
all: libmdRightFielder.so
cp -fp ../Include/mdRightFielder.h ../../util/mdEnums.h libmdRightFielder.so $(SHIP)
if [ `uname` = HP-UX ] ; \
then \
/bin/mv -f $(SHIP)/libmdRightFielder.so $(SHIP)/libmdRightFielder.sl ; \
fi
clean:
rm -f *.o *.so *.sl deps
rm -f core core.[0-9]*
$(APIOBJ): CXXFLAGS+=$(COMPILER_FLAGS_1)
$(PCREOBJ): CXXFLAGS+=$(COMPILER_FLAGS_2)
MARYOBJS = $(APIOBJ) $(PCREOBJ)
libmdRightFielder.so: \
$(MARYOBJS)
-$(CXX) $(CXXFLAGS) $(INCL) $(SHARED) $^ -o $# $(LDLIBS)
mary:
%.o : %.cpp # cancel implicit CPP compilation rule
%.o : %.cpp
$(CXX) $(CXXFLAGS) $(INCL) $(PIC) $< -o $# -c
%.o : %.c # cancel implicit C compilation rule
%.o : %.c
$(CC) $(CFLAGS) $(INCL) $(PIC) $< -o $# -c
endif