I am trying to compile my source files to a static library, however, it doesn't seem to want to work. Here is the code:
#-----------------------------------------------------------------------------
# Usage of make file
#-----------------------------------------------------------------------------
# Clean operation:
# make -f MakeClient clean
#
# Make operation:
# make -f MakeClient
#
#
#OBJ = $(SRC:.cpp=.o)
OBJ_DIR = ./obj
OUT_DIR= ../lib
OUT_FILE_NAME = libclient.a
# include directories
INCLUDES=-I. -I../common -I../../depends -I../../depends/zlib
# C++ compiler flags (-g -O2 -Wall)
CXXFLAGS := -Wall -Wextra -pedantic-errors -std+c++0x
# compiler
CCC = g++
# Enumerating of every *.cpp as *.o and using that as dependency
$(OUT_FILE_NAME): $(patsubst %.cpp,$(OBJ_DIR)/%.o,$(wildcard *.cpp))
$(CCC) -o $(OUT_DIR)/$# $^ -static $(LIB_DIR) $(LIBS) -std=c++11
#Compiling every *.cpp to *.o
$(OBJ_DIR)/%.o: %.cpp dircreation
$(CCC) -c $(INCLUDES) $(CCFLAGS) -o $# $<
dircreation:
#mkdir -p $(OUT_DIR)
#mkdir -p $(OBJ_DIR)
.PHONY : clean
clean:
rm -f $(OBJ_DIR)/*.o $(OUT_DIR)/$(OUT_FILE_NAME) Makefile.bak
The problem seems to be recognising that I'm using C++11 since the actual code does not compile.
Any ideas?
Replace CCFLAGS with CXXFLAGS, or vice versa.
And the flag is spelled -std=c++0x (thanks, #Pixelchemist).
Related
I have a Makefile which is minimal, yet complete. It is the following:
OUT = example
INSTALL_DIR = /usr/local/bin
OBJECT = ./obj
SOURCE = ./src
SRC := $(shell find $(SOURCE) -name *.cc)
OBJ := $(SRC:%=$(OBJECT)/%.o)
DEPS := $(OBJ:.o=.d)
INC_DIRS := $(shell find $(SOURCE) -type d)
INC_FLAGS := $(addprefix -I,$(INC_DIRS))
CC = gcc
CFLAGS = -pipe -fmodules-ts -std=c++2a
DEBUG_FLAGS := $(CFLAGS) -g -Wall -Wextra
RELEASE_FLAGS := $(CFLAGS) -O3 -flto
debug: $(OBJ)
#echo "Building the DEBUG binary..."
#$(CC) $(OBJ) -o $(OUT) $(DEBUG_FLAGS)
#echo "The binary was built successfully!"
release: $(OBJ)
#echo "Building the RELEASE binary..."
#$(CC) $(OBJ) -o $(OUT) $(RELEASE_FLAGS)
#echo "The binary was built successfully!"
install: $(OUT)
#cp $(OUT) $(INSTALL_DIR)
uninstall:
#rm $(INSTALL_DIR)/$(OUT)
$(OBJECT)/%.cc.o: %.cc
#mkdir -p $(dir $#)
#echo "Building $#..."
#$(CC) $(CFLAGS) -c $< -o $#
.PHONY: clean
clean:
rm -rf $(OBJECT) $(OUT)
-include $(DEPS)
There is a directory called "src" which includes the source files. When I'm running make, I will get a compilation error about having to first create modules before using them. If I do create them manually, then I will be able to use "Make" and it will work then it will work. Is there a way to automatically create them?
I recommend using g++-11 instead of just gcc, since versions <=10 do not really include module support asides from the deprecated TS. Then also, use flag -std=c++20.
Also, I have (painful) experience using dependency files with gcc, since that particular feature is not really fully implemented. Last I checked (beginning of nov '21) the dependency files don't actually do anything as pertains to modules.
That being said, what you write should work. And it would, if the compiler-support for modules was finished.
I'm having a little trouble adapting a makefile I found here. What I have is below. When I run it, I get hundreds of "undefined reference to" errors, mostly complaining about the inability to find things in UnitTest. For example, the first is
/home/t/pf/test/main.cpp:63: undefined reference to `UnitTest::RunAllTests()'
Why is this happening? Does this have something to do with how the dependencies are being automatically generated?
Here's the makefile:
# output binary
BIN := main
# source files
SRCS := \
main.cpp test_resamplers.cpp test_rv_eval.cpp test_rv_samp.cpp
# intermediate directory for generated object files
OBJDIR := .o
# intermediate directory for generated dependency files
DEPDIR := .d
# object files, auto generated from source files
OBJS := $(patsubst %,$(OBJDIR)/%.o,$(basename $(SRCS)))
# compilers (at least gcc and clang) don't create the subdirectories automatically
$(shell mkdir -p $(DEPDIR))
$(shell mkdir -p $(dir $(OBJS)) >/dev/null)
# C++ compiler
CXX := g++
# linker
LD := g++
# C++ flags
CXXFLAGS := -std=c++11
# C/C++ flags
CPPFLAGS := -g -Wall -Wextra -pedantic -I/usr/local/include/UnitTest++ -I/usr/include/eigen3 -I../include
# linker flags
LDFLAGS := "-L../bin" "-L/usr/local/lib"
# flags required for dependency generation; passed to compilers
DEPFLAGS = -MT $# -MD -MP -MF $(DEPDIR)/$*.Td
# libraries
LDLIBS := -lpf -lUnitTest++
# compile C++ source files
COMPILE.cc = $(CXX) $(DEPFLAGS) $(CXXFLAGS) $(CPPFLAGS) -c -o $#
# link object files to binary
LINK.o = $(LD) $(LDFLAGS) $(LDLIBS) -o $#
# precompile step
PRECOMPILE =
# postcompile step
POSTCOMPILE = mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d
all: $(BIN)
.PHONY: clean
clean:
$(RM) -r $(OBJDIR) $(DEPDIR)
.PHONY: help
help:
#echo available targets: all clean
$(BIN): $(OBJS)
$(LINK.o) $^
$(OBJDIR)/%.o: %.cpp
$(OBJDIR)/%.o: %.cpp $(DEPDIR)/%.d
$(PRECOMPILE)
$(COMPILE.cc) $<
$(POSTCOMPILE)
.PRECIOUS = $(DEPDIR)/%.d
$(DEPDIR)/%.d: ;
-include $(DEPS)
All your undefined references must appear when line $(LINK.o) $^ is reached, this message is a link problem.
with g++ the link order matters see link order. I would try replacing
# link object files to binary
LINK.o = $(LD) $(LDFLAGS) $(LDLIBS) -o $#
by
# link object files to binary
LINK.o = $(LD) $(LDFLAGS) -o $#
and
$(BIN): $(OBJS)
$(LINK.o) $^
by
$(BIN): $(OBJS)
$(LINK.o) $^ $(LDLIBS)
I have a makefile where I am working with both C source and CPP source. Below is a snippet of code from the makefile. Is there a way to combine the following two targets to compile both filetypes?
#definitions
OBJ_DIR := obj
DEP_DIR := dep
CXX := g++
DEBUG := -g -O0
OPT := -std=c++11 -Wextra -Wall -pthread
LFLAGS = $(DEBUG) $(OPT) $(INC)
CFLAGS = $(LFLAGS) -c
#auto-dependency generation (part 1)
DEP_FLAGS = -MT $# -MMD -MP -MF $(DEP_DIR)/$*.Td
POSTCOMPILE = #mv -f $(DEP_DIR)/$*.Td $(DEP_DIR)/$*.d && touch $#
#compile object files from CPP source
$(OBJ_DIR)/%.o: %.cpp $(DEP_DIR)/%.d
$(CXX) $(CFLAGS) $(DEP_FLAGS) $< -o $#
$(POSTCOMPILE)
#compile object files from C source
$(OBJ_DIR)/%.o: %.c $(DEP_DIR)/%.d
$(CXX) $(CFLAGS) $(DEP_FLAGS) $< -o $#
$(POSTCOMPILE)
#auto-dependency generation (part 2)
$(DEP_DIR)/%.d: ;
.PRECIOUS: $(DEP_DIR)/%.d
include $(wildcard $(DEP_DIR)/*.d)
I have tried to use the wildcard function with a variety of different formatting using second expansion but to no avail.
I am using Make 4.2. The auto-dependency generation code was taken from http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/.
Thanks in advance
Using the right variables as well as the define, call and eval features, the following is possible:
EXT := c cpp
define rule =
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.$(1)
$$(COMPILE.$(1)) $$< -o $$#
endef
$(foreach ext, $(EXT), $(eval $(call rule,$(ext)))) # NO SPACE before $(ext)!!!
make has implicit variables and rules, especially many COMPILE.* rules (you can see them all by issuing the shell command make -p | grep 'COMPILE.* ='):
COMPILE.c = $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
COMPILE.cpp = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
CPPFLAGS is used for preprocessor flags (cpp is the preprocessor executable in the GNU GCC toolchain). TARGET_ARCH is empty on most platforms by default.
Here is a full yet minimalist working Makefile with better auto-dependency generation (note that putting the .d files in a folder separate from the .o pointlessly complicates the makefile):
TARGET := executable
EXT := c cpp
SRC_DIR := .
OBJ_DIR := obj
DEP_DIR := dep
CPPFLAGS = -MMD -MP -MF $(#:$(OBJ_DIR)/%.o=$(DEP_DIR)/%.d)
CFLAGS := -Wall -Wextra -pthread
CXXFLAGS := -std=c++11 $(CFLAGS)
LDFLAGS := -pthread
SOURCE := $(foreach ext, $(EXT), $(wildcard $(SRC_DIR)/*.$(ext)))
OBJECT := $(SOURCE:$(SRC_DIR)/%=$(OBJ_DIR)/%.o)
DEPEND := $(OBJECT:$(OBJ_DIR)/%.o=$(DEP_DIR)/%.d)
define rule =
$(OBJ_DIR)/%.$(1).o: $(SRC_DIR)/%.$(1) | $(OBJ_DIR) $(DEP_DIR)
$$(COMPILE.$(1)) $$< -o $$#
endef
.PHONY: all clean
all: $(TARGET)
$(TARGET): $(OBJECT)
$(CXX) $(LDFLAGS) $^ -o $#
$(foreach ext, $(EXT), $(eval $(call rule,$(ext))))
$(OBJ_DIR) $(DEP_DIR):
mkdir -p $#
-include $(DEPEND)
clean:
$(RM) -r $(TARGET) $(OBJ_DIR) $(DEP_DIR)
Also note that I chose to add the original source file extension (c or cpp) to the object file name (.c.o or .cpp.o) to tackle the case where we could encounter source files with different extension but with the same name.
I have the makefile given below. When I do make I get the following error
cc -c -o timing.o timing.c
test_c.c:5:17: fatal error: test.h: No such file or directory
#include "test.h"
I have manually verfied that test.h is present in ../include path. I am not sure why this is not finding the header file.It would be great if someone could help.Also I would expect g++ instead of cc
# Makefile template for shared library
CXX = g++ # C++ compiler
CXXFLAGS = -fPIC -Wall -Wextra -O2 -g -I../include #CXX flags
LDFLAGS = -lboost_system -shared # linking flags
RM = rm -f # rm command
TARGET_LIB = libtest.a # target lib
C_SRCS := test_a.c test_b.c
CPP_SRCS := test_c.cpp test_d.cpp
OBJS := $(C_SRCS:.c=.o) $(CPP_SRCS:.cpp=.o)
.PHONY: all
all: ${TARGET_LIB}
$(TARGET_LIB): $(OBJS)
$(CXX) $(CXXFLAGS) ${LDFLAGS} -o $# $^
.PHONY: clean
clean:
-${RM} ${TARGET_LIB} ${OBJS}
~
You have not written a rule for building timing.o from timing.c, so Make uses the default rule it has for that.
But that rule uses CFLAGS, not CXXFLAGS. The CXXFLAGS variable appears in the rule for building object files from C++ sources.
So modify CFLAGS instead of CXXFLAGS, and it should work.
I have created a makefile for a library I am compiling.
I have already got the makefile working on windows and linux , but there is a different makefile for each OS.
How could I allow this to work on both OS without hardcoding the path to the boost library and boost headers below:
Do I need to add the boost folder to the path variable? do I need to add the library directory to some OS variable?
makefile windows:
# source files.
SRC = protoService.cpp protocolBaseServer.cpp client.cpp
OBJ = $(SRC:.cpp=.o)
OUT = ../libutils.a
# include directories
INCLUDES = -I. -I../include/ -IC:\boost_1_59_0\
# C++ compiler flags (-g -O2 -Wall)
CCFLAGS = -g -MD -MP -std=c++0x -Wall -c
# compiler
CCC = g++
# library paths
LIBS = -LC:\boost_1_59_0\libs -lboost_serialization
# compile flags
LDFLAGS = -g
.SUFFIXES: .cpp
default: $(OUT)
.cpp.o:
$(CCC) $(INCLUDES) $(CCFLAGS) $< -o $#
$(OUT): $(OBJ)
ar rcs $(OUT) $(OBJ)
#depend: dep
#dep:
# makedepend -- $(CFLAGS) -- $(INCLUDES) $(SRC)
clean:
rm -f $(OBJ) $(OUT) Makefile.bak
-include $(DEPS:%.o=%.d)
makefile linux:
# source files.
SRC = protoService.cpp protocolBaseServer.cpp client.cpp
OBJ = $(SRC:.cpp=.o)
OUT = ../libutils.a
# include directories
INCLUDES = -I. -I../include/ -I/usr/local/include -I/usr/share/boost_1_58_0/
# C++ compiler flags (-g -O2 -Wall)
CCFLAGS = -g -MD -MP -std=c++0x -Wall -c
# compiler
CCC = g++
# library paths
LIBS = -L/usr/share/boost_1_58_0/lib/ -lboost_serialization
# compile flags
LDFLAGS = -g
.SUFFIXES: .cpp
default: $(OUT)
.cpp.o:
$(CCC) $(INCLUDES) $(CCFLAGS) $< -o $#
$(OUT): $(OBJ)
ar rcs $(OUT) $(OBJ)
#depend: dep
#dep:
# makedepend -- $(CFLAGS) -- $(INCLUDES) $(SRC)
clean:
rm -f $(OBJ) $(OUT) Makefile.bak
-include $(DEPS:%.o=%.d)
Make passes environment variables to the makefile processor, so you can create make variables based on them.
INC_PATHS := ../include/ .
LIBS += boost_serialization
ifeq ($(OS),"Windows_NT")
INC_PATHS += ../include/ C:/boost_1_59_0/libs
LIBS += boost_serialization
else
INC_PATHS += /usr/local/include /usr/share/boost_1_58_0/lib/
endif
And then
INCLUDES = $(prepend -I,$(INC_PATHS))
or something like that. I'm not in front of make to ensure the syntax is exactly correct, but it should get you moving in the right direction.