Can't run program after putting the compiled file to the folder - c++

In my Makefile I'm trying to specify, that I want to save the compiled executable file to /dvoram64/ folder. Before, when I tried to save it diretly to / everything worked all right, but now I get this message after calling make run:
ubuntu#pa2:~/Project$ make run
Makefile:37: warning: overriding commands for target `dvoram64/main'
Makefile:34: warning: ignoring old commands for target `dvoram64/main'
make: Circular dvoram64/main <- dvoram64/main dependency dropped.
mkdir -p dvoram64
g++ -Wall -pedantic -Wno-long-long -O0 -ggdb -g -c src/main.cpp -o dvoram64/main
./dvoram64/main
make: execvp: ./dvoram64/main: Permission denied
make: *** [run] Error 127
My Makefile looks like this:
#macros
CC=g++
CCFLAGS=-Wall -pedantic -Wno-long-long -O0 -ggdb -g
LBFLAGS=-lncurses -pthread
Remove=rm -rf
Objects=dvoram64/main
Doxygen=Doxyfile
RUN=./dvoram64/main
CPATH=objects/
#generates final binary and documentation
all: $(Objects) $(Doxygen)
make compile
make doc
#build into final binary
compile: $(RUN)
#run program
run: $(RUN)
$(RUN)
clean:
$(Remove) doc/
$(Remove) dvoram64
#generate documentation in '<login>/doc' folder
doc: $(Doxygen) src/*
( cd src | doxygen $(Doxygen))
#rules to make objects ----------------------------------------------------------------------------------
$(RUN): $(Objects)
$(CC) $(CCFLAGS) $(Objects) -o $(RUN) $(LBFLAGS)
dvoram64/main: src/main.cpp
mkdir -p dvoram64
$(CC) $(CCFLAGS) -c src/main.cpp -o dvoram64/main
Could anybody tell me, what causes that and how to fix it?

You have several problems. First:
RUN=./dvoram64/main
$(RUN): $(Objects)
$(CC) $(CCFLAGS) $(Objects) -o $(RUN) $(LBFLAGS)
dvoram64/main: src/main.cpp
mkdir -p dvoram64
$(CC) $(CCFLAGS) -c src/main.cpp -o dvoram64/main
You have two rules for the same target(dvoram64/main). Which do you want to use? Why do you have two? Remove one of them.
Next:
Objects=dvoram64/main
RUN=./dvoram64/main
$(RUN): $(Objects)
...
You have two variables for (essentially) the same thing, which is untidy but not illegal. But You make one the prerequisite of the other. A thing cannot be it's own prerequisite, and Make must correct the error for you. You should rethink this.
Next:
RUN=./dvoram64/main
run: $(RUN)
$(RUN)
dvoram64/main: src/main.cpp
mkdir -p dvoram64
$(CC) $(CCFLAGS) -c src/main.cpp -o dvoram64/main
You have lost track of whether dvoram64/main should be an object file or an executable file. You have two rules to build it; one builds an executable, the other an object. You name it main, which sounds like an executable file, but you put that name in a variable called Objects. And in the end you build an object file and try to execute it.
You can save yourself some trouble by keeping the makefile as free of redundancy as possible. And when the big target fails, try the little targets one at a time to narrow nown the scope of the problem.

Related

How to improve my makefile in C to move object files and compile even if there are errors?

I created the following makefile:
#COMPILER
CC=gcc
CFLAGS=-I./include/ -L. -Wl,-rpath=. -Wall
CORFLAGS=-I./include/ -c -ansi -pedantic-errors -Wall -Wextra -g
COFLAGS=-I./include/ -Wall -Werror -fpic -c
CSOFLAGS=-shared
#vpath
vpath %.h ./include/
vpath %.c ./test/
vpath %.c ./source/
vpath %.o ./obj/
#PATH
SOURCE=./source/
OUT=-o ./obj/$#
TEST=./test/
OBJPATH=./obj/
#LISTS
CFILESWP=$(wildcard ./source/*.c)
TFILESWP=$(wildcard ./test/*.c)
CFILES=$(notdir $(CFILESWP))
TFILES=$(notdir $(TFILESWP))
TOFILES=$(TFILES:.c=.o)
OFILES=$(CFILES:.c=.o)
OFILESWP=$(addprefix ./obj/,$(OFILES))
NAMES=$(TOFILES:_test.o=)
HFILES=$(CFILES:.c=.h)
.PHONY: clean debug release all
debug: CSOFLAGS+=-g
debug: libds.so
release: CSOFLAGS+=-O2
release: libds.so
test: $(NAMES)
all: libds.so $(NAMES)
%: %_test.c libds.so
$(CC) $(CFLAGS) -o $# $< -lds -g
#SHARED LIBRARY
libds.so: $(OFILES)
$(CC) $(CSOFLAGS) -o libds.so $(OFILES)
#OBJFILES
%.o: %.c %.h
$(CC) $(COFLAGS) -o $# $< -g
#CLEAN
clean:
rm -f *.o $(OBJPATH)*.o
rm -f $(NAMES) libds.so
My make file creates a shared library which called libds.so on make command and creates compiled executables on make test command.
it takes source files called TARGET.c from /source/ directory a.k.a stack.c, queue.c, cbuffer.c and compiles them togeher with their test files from /test/ directory aka stack_test.c, queue_test.c, TARGET_NAME_test.c.
All the .h files are located in the /include/ directory.
and there is also a /obj directory which should contains all the object files which created after running the makefile.
How can I make this makefile better?
How can I move all .o files to /obj directory after each run of make?
Is it possible to create each "project" without the need to compile ALL the targets?
I mean, can I write make, which will create the shared library, and then write create stack and it'll create only executable of stack which compiles /source/stack.c, test/stack_test, include/stack.h and all other associated .h files which appear to be inside the code of the source files.
Can I somehow force the makefile to run and compile only the projects that can be compiled and not to stop the "making", the compilation of the files just because several projets that have syntax errors inside of them or some other errors?
For example:
If I have the following projects: stack.c, queue.c, cbuffer.c
and cbuffer cannot be compiled because something is wrong with its code.
I want to be able to run make and make test and compile the other projects that can be compiled like stack and queue and just show me the compilation error of cbuffer but not to stop the make process.
Thanks.

How to make an object file in a different folder with c++ and a makefile

When I run my code I get the error
g++ -c -o main.o main.cpp
g++ -I -o obj/main.o -lm
g++ error: obj/main.o: No such file or directory
makefile:21: recipe for target 'main' failed
make: *** [main] Error 1
In my file structure I have a folder with everything in it so I am trying to make some subdirectories and organize everything a little bit. I am trying to get the object file (main.o) to go into an obj folder instead of staying in the base folder as it currently is.
I can't figure out what is going wrong in my makefile and can't find where some of this is being executed and am extremely new to c++ and make. My code is pasted below.
IDIR=../include
CC = g++
CFLAGS = -I
LDIR = ../lib
ODIR= obj
LIBS = -lm
_DEPS = add.h multiply.h
DEPS = $(patsubst %, $(IDIR)/%,$(_DEPS))
_OBJ = main.o
OBJ = $(patsubst %, $(ODIR)/%,$(_OBJ))
$(ODIR)/%.o: $(OBJ)
$(CC) -c $(CFLAGS) $< -o $#
main: $(_OBJ)
$(CC) $(CFLAGS) -o$(OBJ) $(LIBS)
.PHONY: clean
clean:
rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~
I haven't read any specific documentation as I have been teaching myself by simply searching the internet for tons of small bits from many different sources. I am using Windows 10 with visual studio code as my compiler and make g++ as my make utility. I apologize for commenting on my own question as this is my first time using Stack Overflow and didn't know I could get in trouble for commenting. I am sorry for causing a mess.
g++ -c -o obj/main.o main.cpp
you must provide the path for the output file

Makefile missing include path Although the path exists and defined

i have make file which i try to make them generic
but it keeps to compline it missing include directory
this is the makefile :
CXX=g++
CPPFAGS= -Wall -O0 -g -std=c++14
INCLUDES = -I/home/vagrant/libuv/include -Isrc
LIBS_DIRS = -L/home/vagrant/libuv/build
LDFLAGS= -lssl -lcrypto
LIB_STATIC = -Wl,--no-as-needed -Bstatic -luv_a -ldl -lpthread
SOURCE = $(wildcard echo.cpp) \
$(wildcard src/*.cpp)
OBJ = $(SOURCE:.cpp=.o)
DEP = $(OBJ:.o=.d)
TARGET = myproj
$(TARGET) : $(OBJ)
$(CXX) $(CPPFLAGS) $(INCLUDES) -o $# $^ $(LIBS_DIRS) $(LDFLAGS) $(LIB_STATIC)
all: $(TARGET)
clean:
rm -f $(OBJ) $(TARGET)
cleandep:
rm -f $(DEP)
.PHONY:all clean cleandep
when i make : make -n :
make -n
g++ -c -o echo.o echo.cpp
g++ -c -o src/base64.o src/base64.cpp
g++ -c -o src/Server.o src/Server.cpp
g++ -c -o src/sha1.o src/sha1.cpp
g++ -c -o src/Client.o src/Client.cpp
g++ -I/home/vagrant/libuv/include -Isrc -o myproj echo.o src/base64.o src/Server.o src/sha1.o src/Client.o -L/home/vagrant/libuv/build -lssl -lcrypto -Wl,--no-as-needed -Bstatic -luv_a -ldl -lpthread
when i invoke make , im getting this error:
make
g++ -c -o echo.o echo.cpp
In file included from src/Server.h:9:0,
from echo.cpp:1:
src/Client.h:6:10: fatal error: uv.h: No such file or directory
#include <uv.h>
^~~~~~
compilation terminated.
make: *** [echo.o] Error 1
but the uv do exist in : /home/vagrant/libuv/include
You have no rule to build your object files: you've only defined a rule to link your object files into a final executable. As mentioned in the comments, adding $(INCLUDES) into that recipe is useless because header file directories are only used during compiling (creating object files) not linking (converting object files and libraries into executables).
Because you haven't defined your own rule to build object files, you're using make's built-in rule. But make's built-in rule doesn't know anything about a variable named INCLUDES, so that variable is not used during compilation. You can easily see this by looking at the compiler commands generated by make.
You need to either (a) create your own rule for compiling object files that uses your personal make variables, or (b) use the normal built-in variables that make expects to be used with its built-in rules.
For (b), as described in the manual, you should take your current CPPFAGS [sic] variable and rename it to CXXFLAGS, take your current INCLUDES variable and rename it CPPFLAGS, take your current LIBS_DIRS variable and rename it LDFLAGS, and take your current LDFLAGS variable and rename it to LDLIBS.
Also just to note, you have DEPS etc. but there is nothing in your makefile that does anything with them or to create them so they're useless.

C++ - Makefile Good Practice

I have a Makefile that works for how I'm using it, but will anyone tell me if what I'm doing is good practice? Or if there is a better, cleaner or more efficient way to achieve the goal I am reaching?
Here is my Makefile Code.
# Object files to either reference or create
OBJECTS = Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
# The executable file that will be created
EXEC = Proj2.out
# The c++ flags to use for compilation
CXXFLAGS = -Wall
# The c++ compiler to use for compilation
CXX = g++
# This section is called on 'make'
# Will call compile, and then call clean
all: compile clean
# Perform action on all object files (May or may not exist)
# The makefile will implicitly compile all .o files needed
# Will also compile them into the EXEC file listed
compile: $(OBJECTS)
$(CXX) $(CXXFLAGS) -o $(EXEC) $(OBJECTS)
# This section is called after compilation is completed
# This will clean all existing .o files listed in the directory
clean:
rm -f *.o
Here is the terminal output when I call make.
g++ -Wall -c -o Proj2.o Proj2.cpp
g++ -Wall -c -o Blackjack.o Blackjack.cpp
g++ -Wall -c -o Deck.o Deck.cpp
g++ -Wall -c -o Card.o Card.cpp
g++ -Wall -c -o Hand.o Hand.cpp
g++ -Wall -c -o Player.o Player.cpp
g++ -Wall -o Proj2.out Proj2.o Blackjack.o Deck.o Card.o Hand.o Player.o
rm -f *.o
Is it good practice to use a Makefile like this? Specifically, am I doing the cleaning part of my Makefile correctly?
You should not make all depend on clean at all. By doing this you are ensuring that every time you run make, you have to recompile everything. If you want to do that then using make is itself useless: just write a shell script that compiles and links your code.
The clean target should be a separate target and if you want to clean your workspace you run make clean explicitly.
The other problem with your makefile is that the link rule lists compile as the target, but it builds $(EXE). It's almost never a good idea to have a rule create a file which is not exactly the target you told make it would build. To ensure this, always use $# as the target to generate. Rewrite it like this:
compile: $(EXE)
$(EXE): $(OBJECTS)
$(CXX) $(CXXFLAGS) -o $# $^

Extending a simple makefile to support different implicit compiler flags

I have been using a makefile that was fairly straightforward. I defined OBJS with a list of .cc files. I set up dependencies and include flags and appended all of those to $CXXFLAGS. It looks something like this:
SRCS = file1.cc file2.cc file3.cc
OBJS = $(SRCS:.cc=.o)
CXXFLAGS=some flags
CXXFLAGS+=some include dirs
$(mylib.so): $OBJS
$CXX -shared -o $# $^
mylib.so uses the CXXFLAGS (implicitly) and everything builds just fine.
I have recently had the need to have mylib_1.so and mylib_2.so, in addition to mylib.so. Each .so depend on all the same .cc files, but the compiler flags are all different (including include directories).
How do I get it so I can set the compiler flags based on the target .so? The problem that I have is that if I set CXXFLAGS more than once it gets overwritten. It's almost like I need an if/else situation.
I tried doing something like setting three different flags, $CXXFLAGS1, $CXXFLAGS2, $CXXFLAGS3, and using those in the line
$(mylib1.so): $OBJS
$CXX $(CXXFLAGS1) -shared -o $# $^
but that does not work.
How do I accomplish what I am trying to do? Is it better to have 3 separate makefiles? I did find a way to get it to work. I can stop using $OBJS and spell out the flags explicitly for each source file but this seems like a horrible idea in terms of scaling to size.
Your CXXFLAGS1 in your example is only used at the stage of creating the .so file, not for compilation of the actual C++ sources (which is what you are trying to do, I assume).
To achieve the above, consider making the Makefile invoke itself 3 times for 3 different targets and pass CXXFLAGS (with different values) as part of MAKEFLAGS or in the command line.
Update: here's an example
all: build-lib1 build-lib2 build-lib3
build-lib1:
$(MAKE) $(MAKEFLAGS) CXXFLAGS="$(CXXFLAGS1)" lib1.so
build-lib2:
$(MAKE) $(MAKEFLAGS) CXXFLAGS="$(CXXFLAGS2)" lib2.so
build-lib3:
$(MAKE) $(MAKEFLAGS) CXXFLAGS="$(CXXFLAGS3)" lib3.so
$(lib1.so): $OBJS
$(CXX) -shared -o $# $^
etc...
Makefiles can have target-specific variable values. Something like:
$(mylib1.so): CXXFLAGS += -lib1flags
$(mylib2.so): CXXFLAGS += -lib2flags
$(mylib3.so): CXXFLAGS += -lib3flags
According to the documentation, the flags will propagate to prerequisite targets.
There is one more special feature of target-specific variables: when
you define a target-specific variable that variable value is also in
effect for all prerequisites of this target, and all their
prerequisites, etc. (unless those prerequisites override that variable
with their own target-specific variable value). So, for example, a
statement like this:
prog : CFLAGS = -g
prog : prog.o foo.o bar.o
will set CFLAGS to ā€˜-gā€™ in the recipe for prog, but it will also set
CFLAGS to ā€˜-gā€™ in the recipes that create prog.o, foo.o, and bar.o,
and any recipes which create their prerequisites.
I would do this with a recursive call to make. I would use two makefiles:
In Makefile:
all: mylib1.so mylib2.so
SRCS := file1.cc file2.cc file3.cc
mylib1.so: $(SRCS)
test -d mylib1 || mkdir mylib1
$(MAKE) -f ../lib.mak -C mylib1 TARGET=mylib1.so CXXFLAGS=-DMYLIB=1
cp mylib1/mylib1.so mylib1.so
mylib2.so: $(SRCS)
test -d mylib2 || mkdir mylib2
$(MAKE) -f ../lib.mak -C mylib2 TARGET=mylib2.so CXXFLAGS=-DMYLIB=2
cp mylib2/mylib2.so mylib2.so
In lib.mak, in the same directory:
VPATH = ..
SRCS := file1.cc file2.cc file3.cc
OBJS := $(SRCS:.cc=.o)
$(TARGET): $(OBJS)
$(CXX) -shared -o $# $^
The second makefile actually builds the library, but only uses one set of CXXFLAGS. The primary makefile calls the first makefile for each version with separate CXXFLAGS and in a separate directory. The VPATH makes it easier to compile source files that aren't in the same directory.
I tested this setup with a dry run,
test -d mylib1 || mkdir mylib1
make -f ../lib.mak -C mylib1 TARGET=mylib1.so CXXFLAGS=-DMYLIB=1
make[1]: Entering directory `/home/depp/Maketest2/mylib1'
g++ -DMYLIB=1 -c -o file1.o ../file1.cc
g++ -DMYLIB=1 -c -o file2.o ../file2.cc
g++ -DMYLIB=1 -c -o file3.o ../file3.cc
g++ -shared -o mylib1.so file1.o file2.o file3.o
make[1]: Leaving directory `/home/depp/Maketest2/mylib1'
cp mylib1/mylib1.so mylib1.so
test -d mylib2 || mkdir mylib2
make -f ../lib.mak -C mylib2 TARGET=mylib2.so CXXFLAGS=-DMYLIB=2
make[1]: Entering directory `/home/depp/Maketest2/mylib2'
g++ -DMYLIB=2 -c -o file1.o ../file1.cc
g++ -DMYLIB=2 -c -o file2.o ../file2.cc
g++ -DMYLIB=2 -c -o file3.o ../file3.cc
g++ -shared -o mylib2.so file1.o file2.o file3.o
make[1]: Leaving directory `/home/depp/Maketest2/mylib2'
cp mylib2/mylib2.so mylib2.so