Compiling C++, organising include files - c++

I'm trying to modify and compile uvccapture on the Raspberry Pi. I got the source from here (it's just a few files).
(I think) the only external files it needs are those of jpeglib which I downloaded from here.
When compiling, where do I put the jpeglib source files? UVCCapture has the following line:
#include <jpeglib.h>
Does that mean I should put the jpeglib source files in the same directory as the UVCCapture source files? That seems messy. How can I set up the compiler (modify the Makefile?), and where should I put the jpeglib files so that I don't need to change the uvccapture include file lines?
And a side question, how come it only includes the .h file and not the .c file? (I'm pretty new to C/C++)
Here is the Makefile:
CC=gcc
CPP=g++
APP_BINARY=uvccapture
VERSION = 0.4
PREFIX=/usr/local/bin
WARNINGS = -Wall
CFLAGS = -std=gnu99 -O2 -DLINUX -DVERSION=\"$(VERSION)\" $(WARNINGS)
CPPFLAGS = $(CFLAGS)
OBJECTS= uvccapture.o v4l2uvc.o
all: uvccapture
clean:
#echo "Cleaning up directory."
rm -f *.a *.o $(APP_BINARY) core *~ log errlog
install:
install $(APP_BINARY) $(PREFIX)
# Applications:
uvccapture: $(OBJECTS)
$(CC) $(OBJECTS) $(XPM_LIB) $(MATH_LIB) -ljpeg -o $(APP_BINARY)
Thanks

The source file (uvccapture.c) doesn't care where the header file (jpeglib.h) is -- at least it shouldn't. The compiler must be told where to look for header files; traditionally, the header files go in some directory like inc_files/, and the compiler is invoked with a command like
gcc -blah -blah -blah -Iinc_files -c -o uvccapture.o uvccapture.c
If you use Make, then Make should execute a command like that. So either edit the makefile, or put the header files in the current directory.
The sane way to use #include in C/C++ is to have source files and header files include header files. That is, in foo.c there will be a couple of lines like:
#include <bar>
#include "baz.h"
and in baz.h there might be a few lines like:
#include <vector>
#include "qux.h"
You almost never see #include foo.c, because it's almost never a good idea.

Related

Headerfiles used by initFile cant be found by make

I'm tying to write a makefile, that should compile (and link) my program. For my program I have to use a bigger Libray with many .h and .cpp files, which comes in a specified filestructure(many other subdirectories)(I'm not allowed to change that stucture)
My main.cpp is included in the first directory which also includes the makefile. This.cpp file includes headers out of the bigger library. And here comes the problem, when i try to "make" the terminal says:" fatal error: .. .h: File or Directory not found" #include ".. .h"
BTW: I'm using Ubuntu 18.04.1 with Gcc and gnu-make
Sooo... I tried several things the last 5 days.
I tried to do it with a dependfile like this:
SRC = datei1.c datei2.c datei3.c datei4.c datei5.c
CC = /usr/bin/gcc
DEPENDFILE = .depend
dep: $(SRC)
$(CC) -MM $(SRC) > $(DEPENDFILE)
-include $(DEPENDFILE)
(Not sure if i made it the right way)
I was thinking of just including every single header file with include, but that would be waaay to much!
I guess the most powerful and useful thing till now was this URL:
Makefile: How to correctly include header file and its directory?.
That nearly described perfectly my problem, but it was just useful to include one single header file and not the whole library.
I guess it could be helpful to know how to correctly include a library. (Maybe try some ways over the PATH?)
Folder Sructure:
myproj
|
|____Makefile
|____main.cpp
|____init.cpp
|____end.cpp
|____init.h
|____end.h
|____Dependencies
|____biggerlib
|____src
|____include
|____biggerLib1
|____biggerLib2
|____biggerLib
|____biggerLibrary.h
|____Lib2.h
|____Lib3.h
|____AnotherDirWithFiles1
|____AnotherDirWithFiles2
|____AnotherDirWithFiles3
|____etc.
#include in file:
#include "biggerLib/biggerLibrary.h"
I really do'nt know what to do anymore!
#Compiler directory
CC = gcc
#directories
SDCC = /home/myname/myproj/Dependencies/biggerlib/src
SDCH = /home/myname/myproj/Dependencies/biggerlib/include/biggerLib # normally ere are a few files and more directories!
#Dependenfile
#DEPENDFILE = .depend
#dep: $(SDCC)
# $(CPP) -MM $(SDCC) > $(DEPENDFILE)
#-include $(DEPENDFILE)
#C-Flags for object-compiling
CFLAGS = -c -I$(SDCH)/.. #ugly!
#Deps including every single one? too much work!
#DEPS = $(SDCH)/biggerlibfile.h
#Libs for Compiler
#LIBS = -lSDCH
#Loading object list
include objects.mk
#Main-target (linking)
$(NAME) : $(OBJECTS)
$(CC) -o $(NAME) #$+ $(LIBS)
#Object-targets
%.o : %.cpp #$(DEPENDFILE) #$(DEPS)
$(CC) -o $# $< $(CFLAGS)
Edit:
The single header file is working, but how do i include all the other header files in the even deeper directories? do I really need to include them all the same way? I need to include every Header behind "include".
I hope u guys understand my problem!:)
Looking forward to your suggestions and tips!

Write a makefile to compile a .h .hpp and .cpp together into an executable

So I have a straightforward problem.
I have files List.hpp, List.h, and test_list.cpp
List.hpp contains function definitions for the List.h file.
The List.h file includes "List.hpp" in the 3rd to last line.
test_list.cpp runs the program and includes "List.h" at the top.
I need a makefile that will compile these into an executable "project.x".
So far have this:
proj2: List.o test_list.o
gcc -o proj2.x List.o test_list.o
List.o:
gcc -c List.hpp
test_list.o:
gcc -c test_list.cpp
clean:
rm *.o proj2.x
However, it results in all kinds of errors, all dealing with lines that have List <T> in them, stating that List does not name a type. I think this is because I am not properly including the header file.
How would I make this makefile?
Judging by the filename extensions and your description, you're compiling C++ code.
You should thus use a C++ compiler: g++. gcc is a C compiler and doesn't know about C++.
You should really just let make compile your code for you, it knows what to do:
proj2: test_list.o
$(CXX) $(LDFLAGS) $(LDLIBS) -o $#
clean:
rm *.o proj2
You don't normally want to compile a header in isolation. It's intended to be included in a source file, and the source file is what you compile.
Given the implicit dependencies in a typical make utility, you can reduce your Makefile a little bit:
proj2.x: test_list.o
g++ -o proj2.x test_list.o
test_list.o: test_list.cpp List.hpp
clean:
-rm *.o proj2.x
At least assuming a reasonably recent version of Make, it'll already know how to compile a .cpp file to get a .o file.
If you're having compiler errors, chances are at least pretty fair that they stem from problems in the code, not in the Makefile. The obvious exceptions would be things like your C++ code failing to link properly, because you used gcc instead of g++ to link it.
As an aside, the header dependency shown in:
test_list.o: test_list.cpp List.hpp
...is something that gcc can generate automatically with the -MM flag. For a tiny Makefile like this one, it's probably not worthwhile to mess with generating dependencies automatically, but for a large one it can be worthwhile. You can even include this as a step in the Makefile itself by running gcc with -MM to generate the dependencies (directing the output to a file) and including that file into a Makefile that does the real work).
More about dependency generation and how to use it in a Makefile:
http://scottmcpeak.com/autodepend/autodepend.html
You don't compile .h or .hpp files. You only compile .c or .cpp files. You probably want something like(Indenting with tabs, not spaces, spaces is a SO and python thing, tabs are a makefile thing):
proj2: list.cpp list.hpp list.h
g++ -o proj2.x list.cpp
clean:
rm proj2.x
Also, in your C file, you will need:
#include "List.h" /* Note the quotes: *
#include <list.h> * won't work */
And likewise for your #include "List.hpp".

Makefile cannot find include path

A Makefile in the subdirectory of my project doesn't see the include path ONLY when it is used from the main Makefile of my project. I don't have much experience with Makefiles and a lot of what I've been reading is pretty confusing. Here is the layout of my directory (with what I have so far since I just started the project):
main/
Inventory/
Item.h
Item.cpp
Makefile
tools/
include/
json/
json.h
jsoncpp.cpp
Makefile
main.cpp
Makefile
Here is the Makefile in the main directory:
INCLUDE = -IInventory/
CC = g++
DEP = tools/jsoncpp.o Inventory/Item.o
Main: main.o $(DEP)
cd tools/ && make
cd Inventory/ && make
$(CC) -o Main main.o $(DEP) $(INCLUDE)
main.o main.cpp
$(CC) -c main.cpp $(INCLUDE)
Here is the Makefile in the tools directory:
INCLUDE = -Iinclude/
CC = g++
jsoncpp.o: jsoncpp.cpp
$(CC) -c jsoncpp.cpp $(INCLUDE)
When I call make from the tools/, it works just fine. But when I call make from the main directory I get this error:
g++ -c -o tools/jsoncpp.o tools/json.cpp
tools/jsoncpp.cpp:76:23: fatal error: json/json.h: No such file or directory
#include "json/json.h"
^
compilation terminated.
Now I partially believe that it can't find the include directory for whatever reason, but the first line in that error is fairly odd to me because of that weird gap between g++ and -c. Since my project will soon get pretty big, how can I fix this?
If it's in -I directive, it should be #include <json/json.h> otherwise #include "include/json/json.h"
EDIT: Include directory is taken from current directory, so in main/ you have to use -Itools/include
Solution: Implicit rules were used so correct variable CXXFLAGS+=$(INCLUDE) must be set for compilation. See: make manual
And the main problem is Main: main.o $(DEP) - files in DEP must exist already otherwise it'll use implicit rules. Later after that cd tools/ && make is done.
#include <json/json.h> <- preprocessor will search in all includes paths
see gcc Include Syntax :
#include <file> This variant is used for system header files. It searches for a file named file in a standard list of system
directories. You can prepend directories to this list with the -I
option (see Invocation).
#include "file" This variant is used for header files of your own program. It searches for a file named file first in the directory
containing the current file, then in the quote directories and then
the same directories used for . You can prepend directories to
the list of quote directories with the -iquote option.

Example makefile for building simple c project recompiling when headers change

Does anyone have a complete makefile that can do the following:
Rebuilds the project if a HEADER file changes
The cpp files are listed in the makefile
The header files are NOT listed in the makefile
The header files are allowed to have different names than the cpp files
Some of the cpp files do not have header files
I have seen instructions for figuring out how to make the make tool figure out header dependencies, but none of these instructions provide anything remotely resembling a working example. A simple example would be as follows: main.cpp C1.cpp C1.h C2.cpp C2.h
CXX = g++
OBJECTS := main.o C1.o C2.o
all: $(OBJECTS)
%.o : %.cpp
$(CXX) $(CPPFLAGS) -Wall -MMD -c $< -o $#
-include *.d
EDIT: As TobySpeight points out, this won't work if you build an object file, rename or delete one of the prerequisite source or header files, then try to rebuild the object file; the .d file will still require the missing file, and the build will fail. I neglected to include lines to deal with that case:
%.h: ;
%.cpp: ;
(This is effective, but crude. The more precise approach is to put some sed commands in the %.o rule, so as to add specific null rules to the .d file, one for each prerequisite, but the sed commands are ugly, and the approach above is good enough for almost all cases.)
You can also use CMake for this. Everything you need to write is:
add_executable (exec main.cpp C1.cpp C2.cpp)

Pre-compiled header warnings on Linux (too short to be a PCH file)

I have a header in my project, called Core.h, that I use as a pre-compiled header:
$(CXX) $(CXX_CFLAGS) -x c++-header Core.h
Which creates a file named Core.h.gch
*#include "Core.h" is the first directive of every source file in the module.
On OS X, it works fine -- my project compiles fine & it compiles pretty fast.
On Linux however, 7 of my 100+ files give the following warning:
warning: Core.h.gch: too short to be a PCH file
Just like every other source file, #include "Core.h" is the first line of these files.
Has anyone ever come across this? Possible causes? Why would it only be a few files that include the PCH that would give the warning ?
I use gcc version 4.1.2 on Linux, 4.2.1 on OSX
Thanks!
EDIT:
Here is basically how I build the library:
.PHONY: all
all: $(MY_PCH) MYLIB.so MYLIB.a
MYLIB.so: $(MY_PCH) $(MY_OBJECTS)
$(CXX) $(MY_OBJECTS) $(CXX_LDFLAGS) -o $#
MYLIB.a: $(MY_PCH) $(MY_OBJECTS)
$(AR) $(ARFLAGS) $# $(MY_OBJECTS)
$(MY_PCH):
$(CXX) $(CXX_CFLAGS) -x c++-header Core.h
Are you using a parallel make? Possibly g++ is trying to read the .gch file while another instance is writing to it.