I'm quite stumped for the past several days I've been trying to solve a casting error inside my VHDL. My code is attached below.
It will evaluate the if statement properly but will not assign the new value to the min or max variables. I know this as I commented out and tested different aspects of the function.
FYI. The type t_battery_data, contains an array of std_logic_vectors(15 downto 0) that are the voltages I'm comparing in the function below.
I'm not sure why it's performing this way. About all I could find in my searching online was to include the, ieee.numeric_std library which I have done.
Still stumped. Any suggestions would be greatly appreciated. Thanks!
function cell_delta_voltage_counts(
bat_data: t_battery_data
) return integer is
constant POS_INFINITY: integer:= 2 ** 16 - 1;
constant NEG_INFINITY: integer:= 0;
variable min: integer range 0 to 2 ** 16 - 1:= POS_INFINITY-5;
variable max: integer range 0 to 2 ** 16 - 1:= NEG_INFINITY;
begin
for i in 0 to NUM_CELLS-1 loop
if (to_integer(unsigned(bat_data.cell_readings(i).voltage)) < min) then
min := to_integer(unsigned(bat_data.cell_readings(i).voltage));
end if;
if (to_integer(unsigned(bat_data.cell_readings(i).voltage)) > max) then
max := to_integer(unsigned(bat_data.cell_readings(i).voltage));
end if;
end loop;
return max - min;
end function cell_delta_voltage_counts;
I don't use a lot of functions, but IIRC if you expect min and max to 'remember' their state between calls, you need to declare them outside the function and declare the function as impure:
variable min: integer range 0 to 2 ** 16 - 1:= POS_INFINITY-5;
variable max: integer range 0 to 2 ** 16 - 1:= NEG_INFINITY;
impure function cell_delta_voltage_counts(
...
I can't see anything wrong here. I tried your code and it works for me in Modelsim DE 10.1c. What simulator are you using?
Here's the code I used when trying your function:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end entity;
architecture sim of test is
constant NUM_CELLS : integer := 2;
type t_reading is record
voltage : std_logic_vector(15 downto 0);
end record t_reading;
type t_readings is array(natural range <>) of t_reading;
type t_battery_data is record
cell_readings : t_readings(0 to NUM_CELLS-1);
end record t_battery_data;
function cell_delta_voltage_counts(
(...)
end function cell_delta_voltage_counts;
begin
process
variable v_battery_data : t_battery_data;
variable v_result : integer := 0;
begin
v_battery_data.cell_readings(0).voltage := x"000a";
v_battery_data.cell_readings(1).voltage := x"001a";
v_result := cell_delta_voltage_counts(v_battery_data);
report "result: " & integer'image(v_result);
wait;
end process;
end architecture;
I used your function exactly as you posted it. The output of simulation is "result: 16" as expected.
Related
I want to show ,the mentioned problem on the title, to you in a function.
finding_first_one(signal a : std_logic_vector(...)) { return bit_number }
Meaning this, lets say, we have a signal '10010100', then return value, bit_number, should be 2. Is there any short way to find it in one cycle. I do not want to scan all the bits per clock.
You can do a for loop in your function.
Be aware that for loop cannot always be implemented on hardware and that it can use A LOT of logic elements.
Try something like this (not tested). index should be equal to 2 in one clock cycle.
architecture behav of test is
signal sig : std_logic_vector(15 downto 0) := x"2224";
signal index : integer;
function finding_first_one (signal a : std_logic_vector()) return integer is
begin
for i in a'low to a'high loop
if a(i) = '1' then
return i;
end if;
end loop;
-- all zero
return -1;
end function;
begin
process (CLK)
begin
if rising_edge(clk) then
index <= finding_first_one(sig);
end if;
end process;
end architecture;
I am having problems with a do while implementation for a sine taylor series. Editing the do loop to do bb = 1, 10 , 2 gives an expected result well within the margin of error, however when running the desired implementation of the do loop (do while(abs(sineseries) - accuracy > 0), will always give an answer equal to 1. So I have narrowed the possibilities down to the do while loop implementation being faulty.
program taylor
implicit none
real :: x
real :: sineseries, nfactsine
real, parameter :: accuracy = 1.e-10
integer :: signum, bb
nfactsine = 1
signum = 1
write(*,*) "Write your input value"
read(*,*) x
sineseries = 0
do while(abs(sineseries) - accuracy > 0)
sineseries = sineseries + (signum*x**bb)/nfactsine
nfactsine = nfactsine*(bb+1)*(bb+2)
signum = -signum
end do
write(*,*) sineseries, sin(x)
end program taylor
The two types of loops are not doing the same thing.
In the loop
do bb=1, 10, 2
...
end do
you have loop control with variable bb. This variable takes the values 1, 3, ..., 9 at iterations as the loop proceeds.
The do while does not have this control: you must replicate the increment of bb manually:
bb=1
do while (...)
...
bb=bb+2
end do
As Pierre de Buyl commented, you also have an error in the termination condition for the indefinite iteration count. The condition initially evaluates as false, so the loop body isn't executed even once.
I found following code in one of the frameworks we are using:
Rem = max (50.0, gm*diamj(i)/vism)
I am looking for the result of Rem. The gm, diamj, vism should be other formula or alphanumeric name.
It's fairly straightforward: it just calculates Rem from a simple formula, and then uses max to limit the result to a value of at least 50, i.e.
Rem = gm*diamj(i)/vism
if (Rem < 50.0)
Rem = 50.0
There is an answer which gives a plausible idea of what the line in the question means. However, an important thing to understand is that it isn't generally possible to isolate the individual lines of code without further context.
That is, from just this single line you cannot tell what will happen.
While there is an intrinsic function max which returns the maximum value of the two arguments we do not know that this function is being used.
Consider the case
function max(a,b)
intrinsic min
max = min(a,b)
end function max
external max
Rem = max(1., 2.)
print*, Rem
end
Here an external function called max is used, not the intrinsic.
There's also
type max
real a,b
end type
type(max) Rem
Rem = max(1., 2.)
print*, Rem
end
Here the default structure constructor for a derived type called max is used. max may even be a generic, or feature other such excitement.
Now, even if max is the intrinsic function, we don't understand the second argument in the question: diamj could be an array or a function. See
function diamj(i)
error stop
end function
Rem = max(1.,diamj(2))
print*, Rem
end
What we can safely say is that max isn't an array. However, there's
integer :: max(2,2)=-1
Rem = max(1,2)
print*, Rem
end
which is very different from
Rem = max(1,2)
print*, Rem
end
Arguably you shouldn't do any of these things but you also shouldn't assume other people haven't.
I am creating a procedure that uses an if statement to perform a decision.
I have four variables: Altitude, Velocity, Angle and Temperature.
The procedure is as follows:
procedure Test3 is
begin
if (Integer(Status_System.Altitude_Measured)) >= Critical_Altitude
and (Integer(Status_System.Velocity_Measured)) >= Critical_Velocity
and (Integer(Status_System.Angle_Measured)) >= Critical_Angle
and (Integer(Status_System.Temperature_Measured)) >= Critical_Temperature
then
DT_Put ("message 1");
else
null;
end if;
end Test3;
This procedure is bassicaly taking the idea that if all the critcal values for the variables are met for each and every variable then it will print a message.
I want to be able to have a shorter way of paring up the statements so I can do the following:
If I have 4 variables: Altitude, velocity, angle and temperature
and I want to have a statement that says, If atleast 3 of these varibles (doesnt matter which three) are all exceeding their critical values
then display a message.
Is it even possible to do this?
I would hate to think that I would have to write each and every possible combination for the if statements.
In short, I want an if statement that says at least 3 of the variables shown are at their criticle value so print a message.
The same would be good for atleast 2 of these variables as well.
First, you should try to use specific types for altitude, velocity, angle and temperature. By using different types you'll leverage strong typing provided by Ada and avoid mistakes such as mixing or comparing altitudes and temperatures. Your example suggests that all of them are Integer. One possible definition could be (there are many others):
type Temperature is digits 5 range -273.15 .. 300.0;
type Angle is digits 5 range -180.0 .. 180.0;
The advantage of such definition is that you define both the range of values and the precision (captors all have a finite precision).
Counting the number of errors is one way do that.
In Ada 2012, you could write:
EDIT
Errors : Natural := 0;
...
Errors := Errors + (if Altitude_Measured > Critical_Altitude then 1 else 0);
Errors := Errors + (if Velocity_Measured > Critical_Velocity then 1 else 0);
Errors := Errors + (if Angle_Measured > Critical_Angle then 1 else 0);
Errors := Errors + (if Temperature_Measured > Critical_Temperature then 1 else 0);
if Errors >= 2 then
...
end if;
Boolean is an enumeration type with values (False, True). As with any enumeration type, the 'Pos attribute can be used to get the position of a value in the list of enumeration literals. Thus, Boolean'Pos(B) equals 0 if B is false, 1 if B is true.
Thus you could say
True_Count := Boolean'Pos(Integer(Status_System.Altitude_Measured) >= Critical_Altitude)
+ Boolean'Pos(Integer(Status_System.Velocity_Measured) >= Critical_Velocity)
+ Boolean'Pos(Integer(Status_System.Angle_Measured) >= Critical_Angle)
+ Boolean'Pos(Integer(Status_System.Temperature_Measured)) >= Critical_Temperature);
I am working on generating a 40 bit length pulse train. I also must be able to adjust the frequency. I tried to make a new low frequency clock and i make a new counter which counts on it's rising edges and give an high output and terminating after 40 bit. It's not working. I tried some other methods. They are not, too.
For example;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity con40 is port(clk:in std_ulogic; q:out std_ulogic);
end entity con40;
architecture Behaviour of con40 is
constant s:std_ulogic_vector:="11111111111111111111111111111111";
signal i:unsigned(4 downto 0):="00000";
signal en:std_logic:='1';
signal reset:std_logic:='0';
begin
q<=s(to_integer(i));
process(reset,clk) is begin
if reset='1' then
i<=(others=>'0');
elsif rising_edge(clk) then
if en='1' then
i<=i+1;
end if;
end if;
end process;
end architecture Behaviour;
There is 32-bit length in this code but i wanna make 40 bit but whatever, this is not working too. I think methods for such a pulse train must be common and they are being used widely. But hey! unluckily i can find nothing useful.
I took the liberty of moving en and reset to port signals, also changed your constant to a recognizable 40 bit value, and specified the range to make it a locally static constant.
The issue with your counter is that it isn't big enough to address 40 bits. You have i specified as a 5 bit value while 40 bits requires a 6 bit counter.
I also added a second architecture here with i as an integer type signal. With i as either an unsigned value or an integer type you likely need to roll over the i counter at 39 ("100111") when the first position is 0 ("000000").
library ieee;
use ieee.std_logic_1164.all;
entity con40 is
port(
reset: in std_ulogic;
clk: in std_ulogic;
en: in std_ulogic;
q: out std_ulogic
);
end entity con40;
architecture foo of con40 is
constant s: std_ulogic_vector (0 to 39) := x"feedfacedb";
signal i: natural range 0 to 39;
begin
q <= s(i);
process (reset, clk)
begin
if reset = '1' then
i <= 0;
elsif rising_edge(clk) and en = '1' then
if i = 39 then
i <= 0;
else
i <= i + 1;
end if;
end if;
end process;
end architecture;
library ieee;
use ieee.numeric_std.all;
architecture behave of con40 is
constant s: std_ulogic_vector (0 to 39) := x"feedfacedb";
signal i: unsigned (5 downto 0);
begin
q <= s(to_integer(i));
process (reset, clk)
begin
if reset = '1' then
i <= "000000";
elsif rising_edge(clk) and en = '1' then
if i = "100111" then
i <= "000000";
else
i <= i + 1;
end if;
end if;
end process;
end architecture;
I also did a quick and dirty test bench:
library ieee;
use ieee.std_logic_1164.all;
entity tb_con40 is
end entity;
architecture foo of tb_con40 is
signal clk: std_ulogic := '0';
signal reset: std_ulogic := '1';
signal en: std_ulogic := '0';
signal q: std_ulogic;
begin
DUT:
entity work.con40
port map (
reset => reset,
clk => clk,
en => en,
q => q
);
CLOCK:
process
begin
for i in 0 to 46 loop
wait for 20 ns;
clk <= not clk;
wait for 20 ns;
clk <= not clk;
end loop;
wait;
end process;
STIMULUS1:
reset <= '0' after 40 ns;
STIMULUS2:
en <= '1' after 60 ns;
end architecture;
Which can demonstrate the correct output:
addendum in response to comment question
The pattern X"FEEDFACEDB" is 40 bits long and was substituted for the 32 all '1's value for constant s to demonstrate that you are actually addressing individual elements of the s array value.
To stop the pulse train fro recurring:
For architecture foo (using an integer type for i):
elsif rising_edge(clk) and en = '1' then
-- if i = 39 then
-- i <= 0;
-- else
if i /= 39 then -- added
i <= i + 1;
end if;
This stops the counter from operating when it reaches 39.
For architecture behave (using an unsigned type for i):
elsif rising_edge(clk) and en = '1' then
-- if i = "100111" then
-- i <= "000000";
-- else
if i /= "100111" then -- added
i <= i + 1;
end if;
end if;
Both architectures behave identically stopping the i counter at 39 ("100111").
The counter can be shown to have stopped by simulating:
Without adding an additional control input the only way to get the pulse stream to occur a second time would be by invoking reseet.
The following code could be a simple implementation to generate pulse trains. This module requires a start impulse (StartSequence) and acknowledges the generated sequence with 'SequenceCompleted'.
Instead of an state machine I use a basic RS flip flop with set = StartSequence and rst = SequenceCompleted_i. I also broke up the process into two processes:
state control - this can be extended to a full FSM if needed
used for counter(s)
Initially, the module emits PULSE_TRAIN(0) by default and also after each sequence generation. So if you want to emit 40 ones otherwise zero set PULSE_TRAIN := (0 => '0', 1 to 40 => '1')
This module is variable in the bit count of PULSE_TRAIN, so I needed to include a function called log2ceil, which calculates the 2s logarithm aka needed bits from PULSE_TRAIN's length attribute.
So in case of 'length = 41 bits Counter_us has a range of (5 downto 0).
entity PulseTrain is
generic (
PULSE_TRAIN : STD_LOGIC_VECTOR
);
port (
Clock : in STD_LOGIC;
StartSequence : in STD_LOGIC;
SequenceCompleted : out STD_LOGIC;
Output : out STD_LOGIC
);
end entity;
architecture rtl of PulseTrain is
function log2ceil(arg : POSITIVE) return NATURAL is
variable tmp : POSITIVE := 1;
variable log : NATURAL := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
signal State : STD_LOGIC := '0';
signal Counter_us : UNSIGNED(log2ceil(PULSE_TRAIN'length) - 1 downto 0) := (others => '0');
signal SequenceCompleted_i : STD_LOGIC;
begin
process(Clock) is
begin
if rising_edge(Clock) then
if (StartSequence = '1') then
State <= '1';
elsif (SequenceCompleted_i = '1') then
State <= '0';
end if;
end if;
end process;
SequenceCompleted_i <= '1' when (Counter_us = (PULSE_TRAIN'length - 1)) else '0';
SequenceCompleted <= SequenceCompleted_i;
process(Clock)
begin
if rising_edge(Clock) then
if (State = '0') then
Counter_us <= (others => '0');
else
Counter_us <= Counter_us + 1;
end if;
end if;
end process;
Output <= PULSE_TRAIN(to_integer(Counter_us));
end;
As what #fru1tbat mentioned, it's not really clear what is "not working" and what you really intend to do. If you would really just want to generate a pulse train, one would think you want to generate a series of alternating '1' and '0', not all '1's like in the code you posted.
Also, the i counter just counts up, and can only be reset to '0' by use of the reset signal, which is fine as long as you intended it that way.
If you'd like to generate a train of '1's and '0's, you'd need something like this (not tested, but should be along these lines):
architecture behaviour of con40 is
constant trainLength:positive:=80;
signal i:unsigned(6 downto 0):=(others=>'0');
...
begin
process(reset,clk) is begin
if reset then
i<=(others=>'0');
q<='0';
elsif rising_edge(clk) then
q<='0'; -- default assignment.
-- Defaults to '0' when if-statement fails.
if i<trainLength then
i<=i+1;
q<=not q;
end if;
end if;
end process;
end architecture behaviour;
This gives you a single-shot pulse train, means there is no way to repeat generation of the pulse train unless you assert the reset signal again. This is fine if it's what you want, otherwise, you'll need more signals to cater for cases where you'd like to re-generate the pulse train without resetting.
Here, I'm assuming you'd like 40 HIGH pulses, which essentially makes the train length 80 clock cycles, not 40. Also, I'm assuming you want a 50% duty cycle, i.e. the HIGH and LOW times are equal. Depending on your requirements, you may need a pulse width that is longer or shorter.
With these assumptions in mind, you'd need at least a 7-bit counter to count 80 clocks. You may think of other better ways to do this as well, but this just comes off the top of my head, and is probably a good place to start.
If your tool doesn't yet support VHDL-2008's enhanced port modes (e.g. ability to read from out-mode ports), then you could declare q as having a buffer mode instead of out. If your tool doesn't support buffer port modes, then you can declare an internal signal and use it for your logic. E.g.:
signal i_q: std_ulogic;
...
i_q<=not i_q; -- use internal signal for logic instead.
q<=i_q; -- drive output from internal signal.
To adjust the frequency, simply supply a higher or lower frequency into your clk input. This can be generated from another PLL, or a frequency divider, or any other oscillating circuitry you have available. Just supply its output into your clk.
Hope this helps.