Why isn't my eval function in my Makefile working? - build

Question

When I try to run the following make file (updated with suggestions below):
# Build Directories
src_dir=src
obj_dir=obj
bin_dir=bin
cc=cl
cc_flags=
configs = dbg rel
# create the directory for the current target.
dir_guard=#mkdir -p $(#D)
# source files
src = MainTest.cpp
define build_template =
# object files - replace .cpp on source files with .o and add the temp directory prefix
obj_$(1) = $$(addprefix $$(obj_dir)/$(1)/, $$(addsuffix .obj, $$(basename $$(src))))
testVar = "wooo"
# build TwoDee.exe from all of the object files.
$$(bin_dir)/$(1)/MainTest.exe : $$(obj_$(1))
$$(dir_guard)
$$(cc) -out:$$# $$(obj_$(1)) -link
# build all of the object files in the temp directory from their corresponding cpp files.
$$(obj): $$(obj_dir)/$(1)/%.obj : $$(src_dir)/%.cpp
$$(dir_guard)
$$(cc) $$(cc_flags) -Fo$$(obj_dir)/$$(1) -c $$<
endef
$(foreach cfg_dir,$(configs),$(eval $(call build_template,$(cfg_dir))))
release: $(bin_dir)/rel/MainTest.exe
debug: cc_flags += -Yd -ZI
debug: $(bin_dir)/dbg/MainTest.exe
$(warning testVar $(testVar))
All I get is:
$ make
Makefile:41: testVar
make: *** No rule to make target `bin/rel/MainTest.exe', needed by `release'. Stop.
You can see from the output that the testVar variable is never set. I made these changes based on my last question: Why doesn't my makefile target-specific variable work?

Answer 1

There are some spaces which confuse Make. Try this:
$(foreach cfg_dir,$(configs),$(eval $(call build_template,$(cfg_dir))))
Also make sure that you specify the right objects to link:
$$(cc) -out:$$# $$(obj_$(1)) -link
And as #Beta pointed out in the comments below, the = in the template definition syntax requires GNU make 3.82 or later. So better omit it from the line:
define build_template