I wrote a small makefile which follows the general structure, creating object files and then linking to create an executable. Here is how it looks..
CXX=g++
CXXFLAGS=-Wall -g
INCLUDES= -I ./
LDFLAGS= -L ./
LIBS= -lcryptopp
SRCS= test.cpp
OBJS= $(SRCS:.cpp=.o)
EXEC=test
all: $(EXEC)
$(EXEC): $(OBJS)
$(CXX) $(CXXFLAGS) $(INCLUDES) -o $(EXEC) $(OBJS) $(LDFLAGS) $(LIBS)
.cpp.o:
$(CXX) $(CXXFLAGS) $(INCLUDES) -c $< -o $#
Cryptopp library(cryptopp) is static. Now when I try to run this makefile, when the first command which tries to create object file runs.. its gives me many errors like this..
test.cpp:289: instantiated from here
./include/algparam.h:322: warning: unused variable 'p'
./include/algparam.h: In member function 'void CryptoPP::AlgorithmParametersTemplate<T>::MoveInto(void*) const [with T = unsigned char]':
In the end, it links all fine and the executable works but how can I get rid of those warnings without removing -wall? I don't have much experience with make and makefiles.
That's not an error, it's a warning. (Technically, you can consider warnings as errors that don't prevent the compiler from finishing its job.)
And the way you fix it is to fix your code. This has nothing to do with the makefile. Delete the variable 'p' from line 322 in ./include/algparam.h. (There was a bit of a hint in the warning message from the compiler.)
for this warning, you can just comment variable p in test.cpp or .h file, because you don't use it, or like this
in your code
{
...
#ifdef _DEBUG_
xxx p;
#endif
...
}
and in your makefile, if you want to use p, just add -D_DEBUG_ in your CXXFLAGS
Related
I have been trying to link the SFML dlls to my windows C++ project, but I can't get it to work. I always end up with:
fatal error: SFML/System.hpp: No such file or directory
I've tried a bunch of things but nothing changes the issue.
Here is my makefile:
PROGRAM = zero_flip
OBJS = src/main.o src/Math.o src/card.o src/game_board.o src/indicator.o src/ui.o
CXX = g++
CXX_FLAGS = -O0 -g -Wall -Wextra -Wno-unused-parameter -Wno-unused-variable
LIB_DIRS = -L./Resources/libs/
LIBS = -lsfml-system -lsfml-graphics -lsfml-window -lsfml-audio
LNK_FLAGS = $(LIB_DIRS) $(LIBS)
DEPS=$(OBJS:.o=.d)
.PHONY: all clean
all: $(PROGRAM)
-include $(DEPS)
%.o: %.cpp
$(CXX) $(CXX_FLAGS) $(LNK_FLAGS) $< -o $#
$(PROGRAM): $(OBJS)
$(CXX) $(CXX_FLAGS) $(LNK_FLAGS) $^ -o $#
clean:
rm -f $(OBJS) $(DEPS) $(PROGRAM) && clear
The "./Resources/libs/" directory contains:
openal32.dll
sfml-audio-2.dll
sfml-audio-d-2.dll
sfml-graphics-2.dll
sfml-graphics-d-2.dll
sfml-system-2.dll
sfml-system-d-2.dll
sfml-window-2.dll
sfml-window-d-2.dll
Can anyone get me unstuck please this is driving me mad.
This is wrong:
%.o: %.cpp
$(CXX) $(CXX_FLAGS) $(LNK_FLAGS) $< -o $#
This rule says it will compile a source file into an object file, but the recipe actually builds a complete executable: it will compile the source file like xxx.cpp then link it into a program named xxx.o. You need to invoke just the compiler here, not the linker, so you should not have $(LNK_FLAGS) and you need to add the -c option to tell the compiler to stop after compiling and not link.
Then you need to add an -I option to the compile line telling the compiler where to find the header files needed during compilation... in this case SFML/System.hpp.
If I have an error on line 1, and I comment out the entirety of the H file, it doesn't always.. update?
It seems to be compiling a past version of the .h file, but if i intentionally put an error in the main.cpp file, then it realizes there are errors in the h file. Also it DOES sometimes show the errors that are just in the h file, but idk if it is after a certain period of time has elapsed
I would just try to put my code in a cpp file attached to the header, but the issue with that is the ugliest error i've ever seen and I'd rather it all stay in the header anyways since it'll only be like 15 lines of code.
Here's the makefile i'm using in case there is some weird thing in this causing the delay.. but I've had this issue just using raw "g++ *.h *.cpp" commands before, so that is probably not the issue. I've struggled with this issue for a long time now and had to put my last HW assignment all in one file because of it
MAINPROG=assignment01
CC=gcc
CXX=g++
CPPFLAGS=-g -std=c++11
LFLAGS=
CFLAGS=-g
TARGET=$(MAINPROG)
CPPS=$(wildcard *.cpp)
LINK=g++ $(CPPFLAGS)
OBJS=$(CPPS:%.cpp=%.o)
%.o: %.cpp
$(CXX) $(CPPFLAGS) -MMD -o $# -c $*.cpp
all: $(TARGET)
$(TARGET): $(OBJS)
$(LINK) $(FLAGS) -o $(TARGET) $^ $(LFLAGS)
clean:
-/bin/rm -rf *.d *.o $(TARGET)
As πάντα ῥεῖ says, it's not normal to compile header files directly. They are incorporated into the compile when they are included into the cpp source.
Your makefile also does not link with the library stdc++ (libstdc++.a). I don't know if this is a problem when linking with g++, but it always is for me with gcc.
Oh, and rm -rf to cleanup! That's fairly aggressive, maybe just rm -f would be better, just in case someone accidentally puts / or .. as the target.
I think you should compile on the command line first, and then sort out the problems with your makefile. It might be worth posting copies of your code.
Generally I will compile simple code with:
gcc -g -Wall -o assignment01 assignment01.cpp -lstdc++
This gives: an exe named "assignment01", with debug info, all warnings, and links with c++ std libs.
I am having a problem when trying to use CPPUTest to test my library.
Everything was fine until i included Eigen library to handle matrix processing.
When i tried to build with g++, Eigen library kept throwing errors:
/eigen3/Eigen/src/Core/util/Memory.h:270:41 error: 'ptr' does not name a type
/eigen3/Eigen/src/Core/CoreEvaluators.h:1655:12 error: expected type-specifier before 'static_cast'
/eigen3/Eigen/src/Core/PlainOBjectBase.h:137:5 error: declaration of 'operator new' as non-function
If Eigen or CPPUTest runs separately, no error is output.
My guess is the two libraries have conflicts at some point.
Really need some helps here. Big thanks.
Edit 1:
This is my Makefile:
CXX = g++ -std=c++0x -lstdc++ CXXFLAGS = -g -Wall -static
-fprofile-arcs -ftest-coverage -I./ -I$(CPPUTEST_HOME)/include LDFLAGS = -L./ -L$(CPPUTEST_HOME)/lib -lCppUTest -lCppUTestExt -pthread CPPUTEST_HOME = ./cpputest/workspace/install USER_CFLAGS = -I
/usr/local/include/eigen3 TARGET = MyLibrary SRCS = MyLibrary.cpp
MyLibraryTest.cpp OBJS = $(SRCS:.cpp=.o) all: $(TARGET) $(TARGET):
$(OBJS) $(CXX) -o $# $^ $(CXXFLAGS) $(LDFLAGS) $(OBJS): $(SRCS)
$(CXX) -c $(CXXFLAGS) $^ %.o: %.cpp $(CXX) -c $(CXXFLAGS) $<
.PHONY: clean clean: rm -f $(TARGET) $(OBJS) *.gcno *.gcov ~ find .
-name ".gcda" | xargs -r r
It appears that CppUTest defines a macro new:
https://github.com/cpputest/cpputest/blob/master/include/CppUTest/MemoryLeakDetectorNewMacros.h#L76
When I #include <Eigen/Core> before #include <CppUTest/TestHarness.h>, I don't get the error you reported (did no further testing, though). Alternatively, you can #undef new after including CppUTest or define CPPUTEST_MEM_LEAK_DETECTION_DISABLED before including CppUTest (that will of course disable leak detection).
The offending line in Eigen is using the placement-new operator (i.e., it does not allocate memory itself), and it's syntax is what throws CppUTest's new macro off.
I am having issue with Makefile that I produced. It consists of one .cpp file with main() inside and I want to create executable from it. While putting in terminal make command I get following:
g++ STutorial.o -o MyExecutable
g++: error: STutorial.o: No such file or directory
g++: fatal error: no input files
While putting first make STutorial.o (.o created) and then make get this:
g++ STutorial.o -o MyExecutable
STutorial.o: In function `main':
STutorial.cpp:(.text+0x47a): undefined reference to `alcOpenDevice'
Firstly, why make does not go from the beginning?
Secondly, why this reference is undefined as if I did not include library, I did that in Makefile aswell as in STutorial.cpp file.
Can you please help me out? I was reading up what could I do wrong and see no clue. (I am beginner and maybe mistake is a rookie one, I apologise in advance but cannot understand it alone)
Makefile:
FLAGS += -std=c++11
CCX=g++
FLAGS +=-c -Wall #for compilation, for warning
FLAGS += -lopenal -lSDL
all: MyExecutable
MyExecutable:
$(CXX) STutorial.o -o MyExecutable
STutorial.o: STutorial.cpp
$(CXX) $(FLAGS) STutorial.cpp
Your makefile should be like this:
CCX=g++
FLAGS +=-c -Wall #for compilation, for warning
LINK_FLAGS += -lopenal -lSDL
all: MyExecutable
MyExecutable: Stutorial.o
$(CXX) STutorial.o -o MyExecutable $(LINK_FLAGS)
STutorial.o: STutorial.cpp
$(CXX) $(FLAGS) STutorial.cpp
Explanation:
Your MyExecutable depends on Stutorial.o which inturn depends on Stutorial.cpp
Now -c flag should be used only with .cpp file to create an object file and not with already created .o file.
Therefore you should have two flags: FLAGS for compiling and LINK_FLAGS for linking libraries during making executable file.
Your executable rule is the issue:
MyExecutable:
$(CXX) STutorial.o -o MyExecutable
It has a target (MyExecutable) and it has a recipe ($(CXX) ...), that all looks good. But what are its prerequisites? MyExecutable does have prerequisites - it needs STutorial.o in order to generate the binary! You need to explicitly tell make about this:
MyExecutable: STutorial.o
$(CXX) STutorial.o -o MyExecutable
Otherwise, you are telling make that you want to build all. all depends on MyExecutable. MyExecutable doesn't depend on anything, so the rule for STutorial.o never gets run.
As for the linker error, you're not linking in the library you need, so you should define something like:
LFLAGS += -lopenal -lSDL
MyExecutable: STutorial.o
$(CXX) STutorial.o $(LFLAGS) -o MyExecutable
You have a few problem in your Makefile starting with:
FLAGS +=-c -Wall #for compilation, for warning
FLAGS += -lopenal -lSDL
You are redefining the FLAGS variable here.
So what you should have is a different variable for your compiler and linker flags:
CFLAGS +=-c -Wall #for compilation, for warning
LDFLAGS += -lopenal -lSDL
Now, for the sake of giving a complete answer, and not solving your immediate problem only I'll try to show how to make the Makefile more flexible:
Start with the sources - you should have a variable for them as well; it's useful when adding/removing source files to/from the project:
SOURCES = STutorial.cpp
define a variable for your object files (this will come in handy at link-time):
OBJ = $(SOURCES:.cpp=.o)
Compile all source files into object files:
.cpp.o:
$(C++) $(CFLAGS) -o $# $<
Link your binary file using the compiled object files:
$(MyExecutable): $(OBJ)
$(C++) $(LDFLAGS) $(OBJ) -o $#
Add a clean command for completeness (removes the binary and object files):
clean:
$(RM) $(EXECUTABLE) $(OBJ)
Now, putting it all together:
CCX=g++
CFLAGS +=-c -Wall -std=c++11#for compilation, for warning
LDFLAGS += -lopenal -lSDL
SOURCES = STutorial.cpp
OBJ = $(SOURCES:.cpp=.o)
all: $(MyExecutable)
$(MyExecutable): $(OBJ)
$(CCX) $(LDFLAGS) $(OBJ) -o $#
.cpp.o:
$(CCx) $(CFLAGS) -o $# $<
clean:
$(RM) $(EXECUTABLE) $(OBJ)
This should allow you to flexibly build, rebuild, clean you project.
This is how you should do:
g++ -std=c++11 -Wall -lopenal -lSDL STutorial.cpp -o MyExecutable
My make file is failing to find my include directory when it tries to remake object files. For example, when I call make tests I get the output:
g++ -c -o sdl_class.o sdl_class.cpp
sdl_class.cpp:9:23: fatal error: sdl_class.h: No such file or directory
#include <sdl_class.h>
^
compilation terminated.
make: *** [sdl_class.o] Error 1
My Makefile is this:
#Originally from: http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/
#But will be heavily modified
IDIR =../include
CC=g++
CFLAGS=-w -I$(IDIR)
#ODIR=obj
LDIR =../lib
LIBS=-lSDL2
_DEPS = sdl_class.h SDL_image.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
OBJ = sdl_class.o tests.o
#OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
%.o: %.cpp $(DEPS)
$(CC) -c -o $# $< $(CFLAGS) $(LIBS)
tests: sdl_class.o tests.o
$(CC) -o $# $^ $(CFLAGS) $(LIBS)
all: $(OBJ)
$(CC) -o $# $^ $(CFLAGS) $(LIBS)
.PHONY: clean
clean:
rm -f *.o *~ core $(IDIR)/*~
My understanding is that when I call make tests, that it should attempt to remake the sdl_class.o file. This should then call the %.o rule, which should try to make the object file by calling something like:
g++ -c -o sdl_class.o sdl_class.cpp -w -I../include -lSDL2
However, this is not the case as it looks like it is calling $(CC) -c -o $# $< $(CFLAGS) $(LIBS), as you can see from above.
Do I have a fundamental misunderstanding about how make builds its rules? Seems likely, this is my first Makefile. Perhaps I am confused on how compilation works in general, as I'm somewhat new to that as well.
I would say that the problem is that one or more of the files ../include/sdl_class.h or ../include/SDL_image.h does not exist. Because of that, make is deciding that your pattern rule does not match (because not all the prerequisites can be found or made) and it defaults to the built-in rule to create object files from .cpp files.
The built-in rules use the make variables CXX for the C++ compiler and CXXFLAGS for the C++ flags: the CC and CFLAGS variables are used for the C compiler. That's why your settings for CFLAGS are being ignored.
If you run make -d sdl_class.o you'll see which file make is looking for and why it decides to not use your pattern rule.
If you rewrite your rules like this it will work better:
%.o: %.cpp
$(CC) -c -o $# $< $(CFLAGS)
sdl_class.o tests.o: $(DEPS)
because make will now complain that the relevant files can't be found or created.
There are other issues, of course. You shouldn't be passing $(LIBS) to your compile command; that belongs only in your link line. And, you should probably stick to the standard variables CXX for the C++ compiler, CPPFLAGS for preprocessor flags like -I and -D, and CXXFLAGS for C++ compiler flags. Also, linker library flags like -L../lib go in LDFLAGS and linker libraries like -lSDL2 go in LDLIBS.
CC/CCFLAGS are for C compilation. You should use CXX and CXXFLAGS for C++. They are used in built-in rules and in the LINK.cc macro, making the Makefile much simpler, and thus less error prone.
CXXFLAGS = -Wall ...
prog : foo.o bar.o
$(LINK.cc) -o $# $^
see Default linker setting in Makefile for linking C++ object files