I am trying to understand the exact actions being taken by a make file (first time working with builds using make).
I want to know whether the make file is intended to be used by BSD make, GNU make or Windows nmake. 1) How can I do this without reading documentation of all three and understanding their differences?
2) After reading several articles, I have come to the conclusion that make is a utility for the primary purpose of building source code into an executable or a DLL or some form of output, something that IDEs usually allow us to do. Makefile is the means of giving instructions to the make utility. Is this right?
3) What is the relation between make and the platform for which the code will be built?
4) The commands that are issued under a dependency line (target:components) are shell commands?
Thanks in advance.
How can I do this without reading documentation of all three and understanding their differences?
Well, most likely, that you will use GNU Make. I believe, it is relatively simple to distinguish Makefiles written for different versions of Make.
AFAIK, GNU Make and BSD Make have many differences, at least in their language syntax. For example, in GNU Make a typical conditional directive looks like:
ifdef VARIABLE
# ...
endif
And in BSD Make it is something like this (though I'm not sure):
.if
# ...
.endif
See also:
How similar/different are gnu make, microsoft nmake and posix standard make?
Use the same makefile for make (Linux) and nmake(Windows)
BSD Make and GNU Make compatible makefile
Makefile is the means of giving instructions to the make utility. Is this right?
Yep, absolutely right.
What is the relation between make and the platform for which the code will be built?
Make is just an utility for tracking dependencies between artifacts to be built and running commands in the proper order to satisfy these dependencies. Which exact commands should be used to accomplish the task is up to the user. Thus you can use Make for cross compilation as well.
The commands that are issued under a dependency line (target : components) are shell commands?
Yes, typically Make spawns a sub-shell which executes the specified recipe.
Related
First, i know that make is used for building the code. But which code?
But what does it mean by building a code, and after executing the make command, what is presented to the user?
Second, how is it different from make build_for_e2e?
What Wikipedia tells about make
Make is a build automation tool that automatically builds executable programs and libraries from source code
Compilation process becomes big and complex in big projects, where numbers of files need to be compiled, with flags and libraries. Where it will become hard for people to compile it one by one. So these types of tools were introduced, there are more similar tools available for same use like cmake, gradle, maven. e2e's Build is also a form of build process, with different form of specifications.
For C people mostly use make. It is helpful for porting software packages in different systems.
How make is used:
As said make is a tool, which will be available in our system, we can execute it by giving command make in the directory which needs to be compiled. Then make looks for Makefile, which is provided in the package directory and it contains information about compilation of the project. Then make as per info gathered from Makefile, it compiles the package.
You can also create Makefile for your project, so that it can be also supported and compiled with make. Simple tutorial for it can be found here. For big projects you can use gnu autotools contains autoconf and automake which will help you to create your all files required by make automatically. You can find tutorial regarding it here and here . These contains some basic information, you can find some advance tutorial regarding autotools, use google for more information on it.
Many a time, I would do the standard ./configure, make, and make install when compiling a package.
However, there are times when I see a package being built with optional make parameters that are specific to that package.
Is there a easy way to list the bundled targets other than going through the Makefile source?
As a general statement, no.
If there are meaningful variables the project should call them out specifically.
The bash (and probably zsh) tab completion support does attempt to get available make targets (with varying degrees of success) if that is of help though.
I'm trying to use the Quadprog++ library (http://quadprog.sourceforge.net/). I don't understand the instructions though.
To build the library simply go through the ./configure; make; make
install cycle.
In order to use it, you will be required to include in your code file
the "Array.hh" header, which contains a handy C++ implementation of
Vector and Matrices.
There are some "configure", and "MakeFile" files, but they have no extension and I have no idea what to do with them. There are also some ".am", ".in" and ".ac" extensions in the folder.
Does this look familiar to anyone? What do I do with this?
(Edit: On Windows.)
This package is built using the autotools. These files you talk to (*.am, *.in...) are because of the tools automake, and autoconf.
Autotools is a de-facto standard in the GNU/Linux world. Not everybody uses it, but if they do you ease the work of package and distribution managers. Actually they should be portable to any POSIX system.
That said, I'm guessing that you are using a non-unix machine, such as Windows, so the configure script is not directly runable in your system. If you insist in keep using Windows, wich you probably will, your options are:
Use MinGW and MSYS to get a minimal build enviroment compatible with autotools.
Use Cygwin and create a POSIX like environment in your Windows.
Create a VS project, add all the source of the library in there, compile and debug the errors they may arise, as if the code had been written by you.
Search for someone that already did the work and distributes a binary DLL, or similar.
(My favourite!) Get a Linux machine, install a cross-compiler environment to build Windows binaries, and do configure --host i686-mingw32 ; make.
This instruction say how can be build an program delivered like a tarball in Linux. To understand take a look on Why always ./configure; make; make install; as 3 separate steps?.
This can be confusing at first, but here you go. Type these in as shown below:
cd <the_directory_with_the_configure_file>
./configure
At this point, a bunch of stuff will roll past on the screen. This is Autoconf running (for more details, see http://www.edwardrosten.com/code/autoconf/index.html)
When it's done, type:
make
This initiates the build process. (To learn more about GNU make, check out Comprehensive gnu make / gcc tutorial). This will cause several build messages to be printed out.
When this is done, type:
sudo make install
You will be asked for the root password. If this is not your own machine (or you do not have superuser access), then contact the person who administers this computer.
If this is your computer, type in the root password and the library should install in /usr/local/lib/ or something similar (watch the screen closely to see where it puts the .so file).
The rest of it (include the .hh file) seems self-explanatory.
Hope that helps!
What is MakeFile in Eclipse? From the documentation:
A makefile is a text file that is referenced by the make command that
describes the building of targets, and contains information such as
source-level dependencies and build-order dependencies. The CDT can
generate a makefile for you, such projects are called Managed Make
projects. Some projects, known as Standard Make projects, allow you to
define your own makefile.
But the explanation does not help me understand what a MakeFile is. I am moving from VisualStudio/C# to Eclipse/C++. Is MakeFile analogous to Visual Studio's Metadata? When do I need to write a MakeFile, and why do I need it besides the C++ code?
[EDIT]
I used to develop on Windows with VS and C#. And now trying Eclipse/C++ on a Mac. I have never build anyone on Linux. So the answer I have read so far does not help explain anything at all.
A makefile in the simplest terms is a file that builds a program. These are normally used from the command line. If you have ever built something on linux you may have run ./configure ; make ; make install. You are using a makefile there.
More info...
https://en.wikipedia.org/wiki/Make_(software)
In simple terms: Make helps you create cross-platform configuration settings in one file, and it will work on surprisingly many platforms, including Windows or Mac OS-es.
Mentioning Windows, you should have Make installed on the computer you're installing on (on Windows, Cygwin and MinGW include Make). It's required only if the user will actually build the code from the source.
But of course, you should include Make code for each different platform (e.g. one for Unix-like, one for Windows, etc.)
How I can make a Makefile, because it's the best way when you distribute a program by source code. Remember that this is for a C++ program and I'm starting in the C development world. But is it possible to make a Makefile for my Python programs?
From your question it sounds like a tutorial or an overview of what Makefiles actually do might benefit you.
A good places to start is the GNU Make documentation.
It includes the following overview "The make utility automatically determines which pieces of a large program need to be recompiled, and issues commands to recompile them."
And its first three chapters covers:
Overview of make
An Introduction to Makefiles
Writing Makefiles
I use Makefiles for some Python projects, but this is highly dubious... I do things like:
SITE_ROOT=/var/www/apache/...
site_dist:
cp -a assets/css build/$(SITE_ROOT)/css
cp -a src/public/*.py build/$(SITE_ROOT)
and so on. Makefile are nothing but batch execution systems (and fairly complex ones at that). You can use your normal Python tools (to generate .pyc and others) the same way you would use GCC.
PY_COMPILE_TOOL=pycompiler
all: myfile.pyc
cp myfile.pyc /usr/share/python/...wherever
myfile.pyc: <deps>
$(PY_COMPILE_TOOL) myfile.py
Then
$ make all
And so on. Just treat your operations like any other. Your pycompiler might be something simple like:
#!/usr/bin/python
import py_compile
py_compile.compile(file_var)
or some variation on
$ python -mcompileall .
It is all the same. Makefiles are nothing special, just automated executions and the ability to check if files need updating.
How i can make a MakeFile, because it's the best way when you distribuite a program by source code
It's not. For example, KDE uses CMake, and Wesnoth uses SCons. I would suggest one of these systems instead, they are easier and more powerful than make. CMake can generate makefiles. :-)
A simple Makefile usually consists of a set of targets, its dependencies, and the actions performed by each target:
all: output.out
output.out: dependency.o dependency2.o
ld -o output.out dependency.o dependency2.o
dependency.o: dependency.c
gcc -o dependency.o dependency.c
dependency2.o: dependency2.c
gcc -o dependency2.o dependency2.c
The target all (which is the first in the example) and tries to build its dependencies in case they don't exist or are not up to date. will be run when no target argument is specified in the make command.
For Python programs, they're usually distributed with a setup.py script which uses distutils in order to build the software. distutils has extensive documentation which should be a good starting point.
If you are asking about a portable form of creating Makefiles you can try to look at http://www.cmake.org/cmake/project/about.html