makefile to compile multiple sources, with different flags - c++

I have the following makefile:
CC = gcc
SRC = source1.c
EXE = source1
FLAGS = -fopenmp
all: $(src)
$(CC) -o $(EXE) $(SRC) $(FLAGS)
clean:
rm $(EXE)
How can I modify it so I can use multiple sources, some of them compiled with the flag -fopenmp, some of them compiled without. Thanks a lot.

This should get you started: Note how -fopenmp gets added just for source2.c
CC=gcc
SRC=source1.c source2.c
OBJ=$(patsubst %.c,%.o,$(SRC))
EXE=source1
FLAGS= -g -O2
source2.o: FLAGS+=-fopenmp
all: $(EXE)
$(EXE): $(OBJ)
$(CC) -o $# $^ $(FLAGS)
%.o: %.c
$(CC) -c -o $# $^ $(FLAGS)
clean:
rm $(EXE)$
Output of make -Bsn:
gcc -o source1.o source1.c -g -O2
gcc -o source2.o source2.c -g -O2 -fopenmp
gcc -o source1 source1.o source2.o -g -O2

You can define for example, EXTFLAGS=$(FLAGS) -fopenmp, and use EXTFLAGS for some rules.

Related

Im working on a makefile which should build a library and then also include that library when building the entire program

INC_DIR = ./include
SRC_DIR = ./src
OBJ_DIR = ./obj
SRC_FILES = $(wildcard $(SRC_DIR)/*.cpp))
H_FILES = $(wildcard $(INC_DIR)/*.cpp)
OBJ_FILES=$(patsubst $(SRC_DIR)/%.cc,$(OBJ_DIR)/%.o,$(SRC_FILES)
TARGET = PT3
CC = g++
CFLAGS = - fPIC -c -Wall -Werror -pedantic -std=c++11 -Wno-c++11-extensions
CPPFLAGS = $(addprefix -I, $(INC_DIR))
clean:
rm -f $(OBJECTS) $(TARGET)
all: $(TARGET)
$(TARGET): $(OBJECTS)
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# $^
%.o: %.cc
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# -c $<
g++ -shared -fPIC -o libtest.so $(OBJECTS)
main.o: main.cc
$(CC) $(CFLAGS) $(CPPFLAGS) -L/pt3/lib -o maintest main.cc -libtest
this is currently what I have and i know its not syntactically right or remotely working but Im getting stuck on creating the shared library so I dont even know what else wouldnt compile.**
INC_DIR = ./include
SRC_DIR = ./src
SRC_FILES = $(sort $(shell find $(SRC_DIR) -name '*.cc'))
OBJ_FILES = $(SRC_FILES:.cc=.o)
TARGET = PT3
CC = g++
CFLAGS = -fPIC -Wall -Werror -pedantic -std=c++11 -Wno-c++11-extensions
CPPFLAGS = $(addprefix -I, $(INC_DIR))
#clean:
# rm -f $(OBJECTS) $(TARGET)
all: $(TARGET)
$(TARGET): $(OBJ_FILES)
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# $^
%.o: %.cc
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# -c $<
libtest.so: $(OBJ_FILES)
$(CC) -shared -fPIC -o $# $^
maintest: main.o libtest.so
$(CC) $(CFLAGS) $(CPPFLAGS) -L. -o maintest main.o -libtest
this is what i rewrote the code to however Im getting a no input files error, but Im not sure if thats coming from a wrong read / failure to get into the required folders, or due to possibly missing a -o or -c?
Ive worked on the code some more following the suggestions and have come to this:
CXX = g++
CXXFLAGS := -Wall -Werror -pedantic -std=c++11 -Wno-c++11-extensions
SRC_FILES = $(wildcard $(SRC_DIR)/*.cpp)
OBJECTS=$(patsubst $(SRC_DIR)/%.cpp,$(OBJ_DIR)/%.o,$(SRC_FILES))
INC_DIR = include
SRC_DIR = src
OBJ_DIR = obj
TEST_DIR = tests
LIB_DIR = lib
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(CXXFLAGS) -fPIC -Iinclude -o $# -c $<
clean:
rm -f $(OBJECTS) $(TEST_DIR)/main.o
$(LIB_DIR)/libtest.so: $(OBJECTS)
#echo frank
$(CXX) -shared -fPIC -o $# $^
$(TEST_DIR)/main.o: $(TEST_DIR)/main.cc
$(CXX) $(CXXFLAGS) -Iinclude -o $# -c $<
maintest: $(TEST_DIR)/main.o $(LIB_DIR)/libtest.so
$(CXX) $(CXXFLAGS) -Llib -Iinclude -o $# $< -ltest
everything seems to compile fine however when running the maintest program it returns an error saying: error while loading shared libraries: libtest.so: cannot open shared object file: No such file or directory
thanks for the suggestions so far I feel like Im on the verge of actually getting the makefile working as intended
You've already written the recipe for the library (which builds it in the working directory -- we can change that later if you want):
g++ -shared -fPIC -o libtest.so $(OBJECTS)
The next step is to put it into a rule:
libtest.so: $(OBJECTS)
g++ -shared -fPIC -o libtest.so $(OBJECTS)
Then clean it up:
libtest.so: $(OBJECTS)
g++ -shared -fPIC -o $# $^
It looks as if you want the executable to be maintest, so let's write a rule for that:
maintest: main.o libtest.so
$(CC) $(CFLAGS) $(CPPFLAGS) -L. -o maintest main.o -ltest
Give that a try. We can make further adjustments once that much works.
EDIT: I see that there are a few other problems in your makefile. Your variables won't work as written. Do you name your source files "foo.cc" or "foo.cpp"?
EDIT: I can see that we'll have to do this in stages.
Step 1. Try this:
CXX = g++
CXXFLAGS := -Wall -Werror -pedantic -std=c++11 -Wno-c++11-extensions
INC_DIR = include
SRC_DIR = src
OBJ_DIR = obj
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(CXXFLAGS) -Iinclude -o $# -c $<
Try to build one or two object files with this, as in make obj/foo.o.
Step 2. Add a rule for main.o, and test it:
$(OBJ_DIR)/main.o: main.cc
$(CXX) $(CXXFLAGS) -Iinclude -o $# -c $<
Step 3. Add a "do nothing" rule for the library, and verify that it builds all of the objects:
SRC_FILES = $(wildcard $(SRC_DIR)/*.cpp)
OBJECTS=$(patsubst $(SRC_DIR)/%.cpp,$(OBJ_DIR)/%.o,$(SRC_FILES))
libtest.so: $(OBJECTS)
#echo doing nothing
Step 4. Change the library rule to actually build the library:
libtest.so: $(OBJECTS)
$(CXX) -shared -fPIC -o $# $^
Step 5. Add a rule to build the test:
maintest: main.o libtest.so
$(CXX) $(CXXFLAGS) -L. -o $# $< -ltest

problem in adding libraries during linking process in Makefile

I am new to Makefiles. I am using opencv and lpthread libraries in a project. The following makefile code dont seems to work. It seems the linking process is failing. Please point out the mistake I made here.
OS: Ubuntu 18.04
CC=g++
LIBS=`pkg-config --cflags --libs opencv`
CXXFLAGS= -c -Wall -std=c++17 -lpthread -march=native -mtune=native -O2
CXXFLAGS2= -Wall -std=c++17 -lpthread -march=native -mtune=native -O2
all: a.out
a.out: main.o brain_starter.o brain_class.o segment_class.o \
logic_core.o data_package_class.o core_class.o
$(CC) $(CXXFLAGS2) $(LIBS) -o a.out main.o brain_starter.o brain_class.o \
segment_class.o logic_core.o data_package_class.o core_class.o
main.o: main.cpp dependency_functions.h
$(CC) $(CXXFLAGS) main.cpp
brain_starter.o: brain_starter.cpp
$(CC) $(CXXFLAGS) brain_starter.cpp
brain_class.o: brain_class.cpp
$(CC) $(CXXFLAGS) brain_class.cpp
segment_class.o: segment_class.cpp
$(CC) $(CXXFLAGS) segment_class.cpp
logic_class.o: logic_class.cpp
$(CC) $(CXXFLAGS) logic_class.cpp
data_package_class.o: data_package_class.cpp
$(CC) $(CXXFLAGS) $(LIBS) data_package_class.cpp
core_class.o: core_class.cpp
$(CC) $(CXXFLAGS) core_class.cpp
clean:
rm -rf *o a.out
I rearranged libs in the linking code and the makefile worked. Here is the working code.
CC=g++
OPENCVLIBS=`pkg-config --cflags --libs opencv`
LIBS= -lpthread
CXXFLAGS= -c -Wall -std=c++17 -march=native -mtune=native -O2
CXXFLAGS2= -Wall -std=c++17 -lpthread -march=native -mtune=native -O2
all: a.out
a.out: main.o brain_starter.o brain_class.o segment_class.o \
logic_core.o data_package_class.o core_class.o
$(CC) $(CXXFLAGS2) -o a.out main.o brain_starter.o brain_class.o segment_class.o logic_core.o data_package_class.o core_class.o $(LIBS) $(OPENCVLIBS)
main.o: main.cpp dependency_functions.h
$(CC) $(CXXFLAGS) $(LIBS) main.cpp
brain_starter.o: brain_starter.cpp
$(CC) $(CXXFLAGS) $(LIBS) brain_starter.cpp
brain_class.o: brain_class.cpp
$(CC) $(CXXFLAGS) $(LIBS) brain_class.cpp
segment_class.o: segment_class.cpp
$(CC) $(CXXFLAGS) $(LIBS) segment_class.cpp
logic_class.o: logic_class.cpp
$(CC) $(CXXFLAGS) $(LIBS) logic_class.cpp
data_package_class.o: data_package_class.cpp
$(CC) $(CXXFLAGS) $(LIBS) $(OPENCVLIBS) data_package_class.cpp
core_class.o: core_class.cpp
$(CC) $(CXXFLAGS) core_class.cpp
clean:
rm -rf *o a.out

SDL Max OSX via Homebrew, Makefile not quite working

I have installed SDL through homebrew, and it works perfectly with my test program if I enter the following command directly in the terminal:
g++ -O3 -g -Wall -Wextra -std=c++1y hello.cpp hello_main.cpp `sdl2-config --cflags --libs` -o hello
but unfortunately my attempts to write a makefile (I will definitely need one) have yielded unsuccessful/unexplained results.
I am following this, but my configuration is different/I am not specifying Cocoa (I don't need to) so I expect that the issues I am encountering are probably due in part to my different requirements:
Compiling SDL on OS X with makefile
Example:
CC=g++
CFLAGS=-c -Wall
SDLFLAGS=`sdl-config --cflags --libs` -framework Cocoa
SOURCES=main.cpp Game.cpp IO.cpp Board.cpp Pieces.cpp Piece.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=tetris
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(OBJECTS) $(SDLFLAGS) -o $#
.cpp.o:
$(CC) $(CFLAGS) $< -o $#
clean:
rm -rf *.o $(EXECUTABLE)
My makefile so far:
CXX = g++
CXXFLAGS = -c -O3 -g -Wall -Wextra -std=c++1y
SDLFLAGS = `sdl2-config --cflags --libs`
SOURCES = hello_main.cpp hello.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECNAME = hello
all: $(SOURCES) $(EXECNAME)
$(EXECUTABLE): $(OBJECTS)
$(CXX) $ (OBJECTS) $(SDLFLAGS) -o $#
.cpp.o:
$(CXX) $(CXXFLAGS) $< -o $#
clean :
-rm -f *.o *.core $(EXECNAME)
In my .hpp header file if I #include <SDL.h> and run the one-liner command, everything is successful. If I try my makefile above, cannot be found, but if I then change the directive into #include <SDL2/SDL.h> the library is discovered. Yet the console output is the following:
g++ -c -O3 -g -Wall -Wextra -std=c++1y hello.cpp -o hello
which is odd.
Running ./hello yields a "permission denied" error, which confirms that the linking and compilation were not successful.
Everyone's system is a little bit different and the questions I've found so far don't help in this case.
I am very close to having this working (but then again, how would I start using this in an IDE? I suppose that as long as I can import the fixed makefile or build from the terminal/edit only from the IDE, I am fine.)
What changes in the makefile do I need to make?
Thank you.
EDIT:
Variation 1:
CXX = g++
CXXFLAGS = -O3 -g -Wall -Wextra -std=c++1y -c
SDLCFLAGS = `sdl2-config --cflags`
SDLLIBFLAGS = `sdl2-config --libs`
SOURCES = hello_main.cpp hello.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECNAME = hello
all: $(SOURCES) $(EXECNAME)
$(EXECUTABLE): $(OBJECTS)
$(CXX) $ (OBJECTS) $(SDLLIBFLAGS) -o $#
.cpp.o:
$(CXX) $(CXXFLAGS) $(SDLCFLAGS) $< -o $#
clean :
-rm -f *.o *.core $(EXECNAME)
I chatted with a friend and figured what was wrong: a bunch of typos and rule oddities. The following works, for anyone out there who needs a basic makefile:
CXX = g++
CXXFLAGS = -O3 -g -Wall -Wextra -std=c++1y
#LDFLAGS = -lSDL2_image
SDLCFLAGS = $(shell sdl2-config --cflags)
SDLLIBFLAGS = $(shell sdl2-config --libs)
SOURCES = hello_main.cpp hello.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECNAME = hello
all: $(EXECNAME)
$(EXECNAME): $(OBJECTS)
$(CXX) $(OBJECTS) $(SDLLIBFLAGS) $(LDFLAGS) -o $#
%.o: %.cpp
$(CXX) -c $(CXXFLAGS) $(SDLCFLAGS) $< -o $#
clean :
-rm -f *.o *.core $(EXECNAME)
You should split your sdl2-config into two - as there are two steps. sdl2-config --cflags should go in the compiler step - thats is the .cpp:.o line in your example. The linking step should be sdl2-config --libs then. The second one seems fine for your case, the additional --cflags there does no harm but is not required.

OpenMP Makefile, -fopenmp won't work

I'm trying to compile my project using a Makefile, but somehow the -fopenmp flag won't work.
Here's the Makefile:
TARGET=isaac
CC=g++
CFLAGS=-Wall -O2 -fopenmp
LDFLAGS=-lm -lpthread -lrt
OBJ=src/main.o src/bhtree.o src/body.o src/configreader.o src/diagnostics.o src/output.o src/quad.o src/timing.o src/vector2.o
isaac: $(OBJ)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJ) $(LDFLAGS)
%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
clean:
rm src/*.o src/*~ isaac
and here is the output when calling "make"
g++ -c -o src/main.o src/main.cpp
g++ -c -o src/bhtree.o src/bhtree.cpp
g++ -c -o src/body.o src/body.cpp
g++ -c -o src/configreader.o src/configreader.cpp
g++ -c -o src/diagnostics.o src/diagnostics.cpp
g++ -c -o src/output.o src/output.cpp
g++ -c -o src/quad.o src/quad.cpp
g++ -c -o src/timing.o src/timing.cpp
g++ -c -o src/vector2.o src/vector2.cpp
g++ -Wall -O2 -fopenmp -o isaac src/main.o src/bhtree.o src/body.o src/configreader.o src/diagnostics.o src/output.o src/quad.o src/timing.o src/vector2.o -lm -lpthread -lrt
the -fopenmp flag is missing when the source files are compiled, so the finished executable is serial, not parallel.
How can I fix this?
The problem is that your rule does not apply at all. You are free to remove
%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
and you'll get the same result as before. That's because some predefined rule is used instead of yours (I'm not great makefile expert though).
The core of the problem is that your rule is for ./*.o files, but you need ./src/*.o for isaac. You can change your rule
src/%.o: src/%.cpp
$(CC) $(CFLAGS) -c $<
Or (better) move all autogenerated staff somewhere from src.

Makefile for shared library that only compiles changed files?

I am working on a project where I am creating a .so object as my output that contains several operators for use in another program. I was given a Makefile that works just fine, except it always recompiles every file whenever I run make. Originally this was not an issue, but now that there are upwards of five or more operators in the library, running make is prohibitively slow. The trouble is that for the life of me, I can't figure out how to change this Makefile into one that behaves the way I want since I've never dealt with Makefiles in this format before:
BOOST_LOCATION=/usr/local/boost_1_54_0
CFLAGS=-pedantic -W -Wextra -Wall -Wno-strict-aliasing -Wno-long-long -Wno-unused-parameter -fPIC -D__STDC_FORMAT_MACROS -Wno-system-headers -isystem -O2 -g -DNDEBUG -ggdb3 -D__STDC_LIMIT_MACROS
INC=-I. -DPROJECT_ROOT="\"$(IN_SOURCE_DIR)\"" -I"$(IN_SOURCE_DIR)/include" -I"$(BOOST_LOCATION)"
LIBS=-L"$(IN_SOURCE_DIR)/lib" -shared -Wl,-soname,libname.so -L. -lm
all:
#if test ! -d "$(IN_SOURCE_DIR)"; then echo "Error. Try:\n\nmake IN_SOURCE_DIR=<PATH TO SOURCE TRUNK>"; exit 1; fi
$(CXX) $(CFLAGS) $(INC) -o plugin.cpp.o -c plugin.cpp
$(CXX) $(CFLAGS) $(INC) -o LogicalFile1.cpp.o -c File1/LogicalFile1.cpp
$(CXX) $(CFLAGS) $(INC) -o PhysicalFile1.cpp.o -c File1/PhysicalFile1.cpp
$(CXX) $(CFLAGS) $(INC) -o LogicalFile2.cpp.o -c File2/LogicalFile2.cpp
$(CXX) $(CFLAGS) $(INC) -o PhysicalFile2.cpp.o -c File2/PhysicalFile2.cpp
### etc.
$(CXX) $(CFLAGS) $(INC) -o libname.so \
plugin.cpp.o \
LogicalFile1.cpp.o \
PhysicalFile1.cpp.o \
LogicalFile2.cpp.o \
PhysicalFile2.cpp.o \
### etc \
$(LIBS)
clean:
rm -f *.o *.so
The biggest issue I have is that there is only one rule (all), and I cannot find an example of a Makefile that does this or how to split it into multiple rules.
In this case, it's actually pretty straightforward. Right now, you just have an all target that's doing all the building. You need to break out the compiler invocations and link step into their own rules, and you should be off to the races:
BOOST_LOCATION=/usr/local/boost_1_54_0
CFLAGS=-pedantic -W -Wextra -Wall -Wno-strict-aliasing -Wno-long-long -Wno-unused-parameter -fPIC -D__STDC_FORMAT_MACROS -Wno-system-headers -isystem -O2 -g -DNDEBUG -ggdb3 -D__STDC_LIMIT_MACROS
INC=-I. -DPROJECT_ROOT="\"$(IN_SOURCE_DIR)\"" -I"$(IN_SOURCE_DIR)/include" -I"$(BOOST_LOCATION)"
LIBS=-L"$(IN_SOURCE_DIR)/lib" -shared -Wl,-soname,libname.so -L. -lm
all: plugin.cpp.o LogicalFile1.cpp.o PhysicalFile1.cpp.o LogicalFile2.cpp.o PhysicalFile2.cpp.o
$(CXX) $(CFLAGS) $(INC) -o libname.so \
plugin.cpp.o \
LogicalFile1.cpp.o \
PhysicalFile1.cpp.o \
LogicalFile2.cpp.o \
PhysicalFile2.cpp.o \
### etc \
$(LIBS)
plugin.cpp.o: plugin.cpp | test
$(CXX) $(CFLAGS) $(INC) -o plugin.cpp.o -c plugin.cpp
LogicalFile1.cpp.o: File1/LogicalFile1.cpp | test
$(CXX) $(CFLAGS) $(INC) -o LogicalFile1.cpp.o -c File1/LogicalFile1.cpp
PhysicalFile1.cpp.o: File1/PhysicalFile1.cpp | test
$(CXX) $(CFLAGS) $(INC) -o PhysicalFile1.cpp.o -c File1/PhysicalFile1.cpp
LogicalFile2.cpp.o: File2/LogicalFile2.cpp | test
$(CXX) $(CFLAGS) $(INC) -o LogicalFile2.cpp.o -c File2/LogicalFile2.cpp
PhysicalFile2.cpp.o: File2/PhysicalFile2.cpp | test
$(CXX) $(CFLAGS) $(INC) -o PhysicalFile2.cpp.o -c File2/PhysicalFile2.cpp
test:
#if test ! -d "$(IN_SOURCE_DIR)"; then echo "Error. Try:\n\nmake IN_SOURCE_DIR=<PATH TO SOURCE TRUNK>"; exit 1; fi
clean:
rm -f *.o *.so
.PHONY: all clean test
From this point, you can simplify further, too. You could consolidate all of the compile lines into a single pattern rule, for example.
If you're willing to use the standard formats and built-in rules for make, you can write your entire makefile as easily as this:
ifeq (,$(wildcard $(IN_SOURCE_DIR)/.))
$(error Try: make IN_SOURCE_DIR=<PATH TO SOURCE TRUNK>)
endif
OBJECTS = plugin.o LogicalFile1.o PhysicalFile1.o LogicalFile2.o PhysicalFile2.o ### etc
BOOST_LOCATION = /usr/local/boost_1_54_0
CPPFLAGS = -DNDEBUG -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I. -DPROJECT_ROOT="\"$(IN_SOURCE_DIR)\"" -I"$(IN_SOURCE_DIR)/include" -I"$(BOOST_LOCATION)"
CXXFLAGS = -pedantic -W -Wextra -Wall -Wno-strict-aliasing -Wno-long-long -Wno-unused-parameter -fPIC -Wno-system-headers -isystem -O2 -g -ggdb3
LDFLAGS = -L"$(IN_SOURCE_DIR)/lib" -L.
LDLIBS = -shared -Wl,-soname,libname.so -lm
all: libname.so
libname.so: $(OBJECTS)
$(LINK.cc) $^ $(LDLIBS) -o $#
clean:
rm -f *.o *.so
.PHONY: all clean