CC = g++
CFLAGS = -Wall
RM = /bin/rm -rf
BIN_DIR =
ifeq "$(DEBUG)" "1"
BIN_DIR = Debug
else
BIN_DIR = Release
endif
OBJS = \
$(BIN_DIR)/Unit.o
$(BIN_DIR)/%.o: src/%.c
#echo Building "$#"
#g++ -c "$<" -o"$#"
all: $(OBJS)
clean:
$(RM) $(BIN_DIR)
.PHONY: all clean
However, when I try to build my project this, it gives me the error:
make: *** No rule to make target 'Release/Unit.o', needed by 'all'. Stop.
I am new to writing makefiles from scratch and so this might be a stupid question, but any help is appreciated!
The problem is here:
$(BIN_DIR)/%.o: src/%.c
#echo Building "$#"
#g++ -c "#<" -o"$#"
I think that's more like this :
$(BIN_DIR)%.o: %.c
$(CC) -o $# -c $< $(CFLAGS)
As Sean Bright already pointed out, changing
#g++ -c "#<" -o"$#"
to
#g++ -c "$<" -o"$#"
also makes the Makefile work for me (ming32-make: GNU Make 3.81)
Since you had the Makefile on the same level as the source file (inside the src directory), your rule were failing.
Related
I have a Makefile which is minimal, yet complete. It is the following:
OUT = example
INSTALL_DIR = /usr/local/bin
OBJECT = ./obj
SOURCE = ./src
SRC := $(shell find $(SOURCE) -name *.cc)
OBJ := $(SRC:%=$(OBJECT)/%.o)
DEPS := $(OBJ:.o=.d)
INC_DIRS := $(shell find $(SOURCE) -type d)
INC_FLAGS := $(addprefix -I,$(INC_DIRS))
CC = gcc
CFLAGS = -pipe -fmodules-ts -std=c++2a
DEBUG_FLAGS := $(CFLAGS) -g -Wall -Wextra
RELEASE_FLAGS := $(CFLAGS) -O3 -flto
debug: $(OBJ)
#echo "Building the DEBUG binary..."
#$(CC) $(OBJ) -o $(OUT) $(DEBUG_FLAGS)
#echo "The binary was built successfully!"
release: $(OBJ)
#echo "Building the RELEASE binary..."
#$(CC) $(OBJ) -o $(OUT) $(RELEASE_FLAGS)
#echo "The binary was built successfully!"
install: $(OUT)
#cp $(OUT) $(INSTALL_DIR)
uninstall:
#rm $(INSTALL_DIR)/$(OUT)
$(OBJECT)/%.cc.o: %.cc
#mkdir -p $(dir $#)
#echo "Building $#..."
#$(CC) $(CFLAGS) -c $< -o $#
.PHONY: clean
clean:
rm -rf $(OBJECT) $(OUT)
-include $(DEPS)
There is a directory called "src" which includes the source files. When I'm running make, I will get a compilation error about having to first create modules before using them. If I do create them manually, then I will be able to use "Make" and it will work then it will work. Is there a way to automatically create them?
I recommend using g++-11 instead of just gcc, since versions <=10 do not really include module support asides from the deprecated TS. Then also, use flag -std=c++20.
Also, I have (painful) experience using dependency files with gcc, since that particular feature is not really fully implemented. Last I checked (beginning of nov '21) the dependency files don't actually do anything as pertains to modules.
That being said, what you write should work. And it would, if the compiler-support for modules was finished.
I'm working on a Makefile that i can use on most of my school projects.
I only did basics makefile before and never had a problem, but for this one i wanted to put some colors etc...
And it relink everytime i make it.
I think the relink come from my echos ? But i'm not sure.
Here is my makefile :
#GENERAL
CC = clang++
FLAGS = -Wall -Wextra -Werror -std=c++98
RM = rm -rf
#PROJET
EXEC = ClapTrap
#FILES
SRCS = ClapTrap.cpp main.cpp
OBJS = $(SRCS:.cpp=.o)
OBJSDIR = objects/
#REGLES
.cpp.o: $(SRCS)
mkdir -p $(OBJSDIR)
echo "$(BLUE)Compiling $^ ..$(CLEAR)"
$(CC) $(FLAGS) -c $< -o $(addprefix $(OBJSDIR), $#)
echo " $(YELLOW)$(addprefix $(OBJSDIR), $#)$(CLEAR) [$(GREEN)OK$(CLEAR)]"
all: $(EXEC)
$(EXEC): $(OBJS)
echo "$(BLUE)========================================$(CLEAR)"
echo "$(BLUE) Compiling binary file ..$(CLEAR)"
echo "$(BLUE)========================================$(CLEAR)"
$(CC) -o $(EXEC) $(addprefix $(OBJSDIR), $^) $(FLAGS)
echo "$(YELLOW)$(EXEC)$(GREEN) is now ready to use !$(CLEAR)"
clean:
#$(RM) $(OBJSDIR)
#echo "$(RED)Cleaning up..$(CLEAR)"
fclean: clean
#$(RM) $(EXEC)
#echo -n "$(RED)$(EXEC)$(CLEAR)"
re: fclean all
.PHONY: all
Thank's for reading !
EDIT :
So i removed SRCS from my .cpp.o rules dependencies, but still relinking.
Here the updated Makefile :
#FILES
SRCS = ClapTrap.cpp main.cpp
OBJS = $(SRCS:.cpp=.o)
OBJSDIR = objects
#REGLES
.cpp.o:
echo "$(BLUE)Compiling $(YELLOW)$^$(BLUE) ..$(CLEAR)"
mkdir -p $(OBJSDIR)
$(CC) $(FLAGS) -c $< -o $#
mv $# $(OBJSDIR)
echo "$(BLUE) - $(YELLOW)$#$(CLEAR) [$(GREEN)OK$(CLEAR)]"
all: $(EXEC)
$(EXEC): $(OBJS)
echo "$(BLUE)========================================$(CLEAR)"
echo "$(BLUE) Compiling binary file ..$(CLEAR)"
echo "$(BLUE)========================================$(CLEAR)"
$(CC) $(FLAGS) $(STD) $(addprefix $(OBJSDIR)/, $(OBJS)) -o $(EXEC)
echo "$(YELLOW)$(EXEC)$(GREEN) is now ready to use !$(CLEAR)"
This is wrong:
$(CC) $(FLAGS) -c $< -o $#
mv $# $(OBJSDIR)
When make runs your recipe it will put the file it expects you to build into the $# automatic variable. If your makefile builds some OTHER file, not the one it asked you to build, then the next time you run make it will see that the file it wants doesn't exist (because you didn't build it, you build some other file) and so it's always out of date.
Your rules must always build exactly the file $#, not some other file.
It's not actually possible to write a makefile that puts targets in a different directory, using suffix rules. They can only create files in the same directory. That's (one reason) why GNU make supports pattern rules which are much more flexible.
If you have to write a POSIX conforming makefile that doesn't support pattern rules, and you want to put the object files in some other directory, all you can do is write out all the targets and their rules explicitly.
I have a problem with the dependencies in my Makefile.
There is no problem with the compilation, it compiles perfectly the good *.cc and *.hh but unfortunately, it does not re-compile the dependencies, thus there is no update in the executable.
Here is my makefile:
EXEC ?= program
SRCS = $(shell find -name *.cc)
DEP = $(SRCS:.cc=.d)
OBJDIR = objs
OBJS = $(SRCS:./%.cc=$(OBJDIR)/%.o)
CXX = g++
CFLAGS = -std=c++14 $(addprefix "-I", $(shell find -type d))
## Clean rule
.PHONY: clean
clean:
rm -rf $(OBJDIR)
rm -f $(EXEC)
$(EXEC) : $(OBJS)
#echo "Linking: $#"
$(CXX) $(OBJS) -o $#
-include $(DEP)
$(OBJDIR)/%.o : ./%.cc ./%.hh
#mkdir -p $(#D)
#echo "Compiling: $<"
#$(CXX) -c $(CFLAGS) -MT $# -MMD -MP -o $# $<
It is probably something related to the flag used by g++ but I do not manage to find the solution;
Thanks in advance for the help that you can provide on this issue,
If you do not specify the filename for the generated dependency files, it is going to be ${#:%.o=%.d} (compiler logic). I.e. your dependency files are in $(OBJDIR) and not in ./ where your makefile expects them to be.
Two alternative solutions:
DEP := $(OBJS:%.o=%.d).
#$(CXX) -c $(CFLAGS) -MT $# -MMD -MP -MF $(<:%.cc=%.d) -o $# $<
I have this Makefile:
OBJS = main_exp_par_auto.o
SOURCE = ../main/main_exp_par_auto.cpp
HEADER = ../Division_Euclidean_space.h ../Find_diameter.h ../Find_k_max.h ../Householder.h ../IO.h ../Mean_variance.h ../Point.h ../Random_generator.h ../Random_kd_forest.h ../Tree.h ../Auto_random_kd_forest.h
OUT = geraf
CXX = g++
FLAGS = -pthread -std=c++0x -DRKD_PAR -O3 -Wall
all: $(OBJS)
$(CXX) $(OBJS) -o $(OUT) $(FLAGS)
make -f makefiles/Makefile_exp_par_auto clean
# create/compile the individual files >>separately<<
main_exp_par_auto.o: main/main_exp_par_auto.cpp
$(CXX) -c main/main_exp_par_auto.cpp $(FLAGS)
.PHONY : all
# clean house
clean:
rm -f $(OBJS)
# do a bit of accounting
count:
wc $(SOURCE) $(HEADER)
and the folder looks like this:
However, I am getting:
gsamaras#gsamaras-A15:/media/gsamaras/a6cd1464-abf1-4a7b-b4a2-61f584d4cb32/gsamaras/code/C++/kd_GeRaF-master/makefiles$ make -f Makefile_exp_par_auto
make: *** No rule to make target `main/main_exp_par_auto.cpp', needed by `main_exp_par_auto.o'. Stop.
This is an old project of mine and that was supposed to be working, how to fix this?
You are invoking it from makefiles directory, whereas main directory is on the same level. It looks for main/main_exp_par_auto.cpp and fails to find it.
Invoke make like that:
make -C /media/gsamaras/a6cd1464-abf1-4a7b-b4a2-61f584d4cb32/gsamaras/code/C++/kd_GeRaF-master -f makefiles/Makefile_exp_par_auto
So I can compile my code (fftw_ex.c) directly with:
login$ gcc -o -g fftw_ex fftw_ex.c -I$TACC_FFTW3_INC -L$TACC_FFTW3_LIB -lfftw3
However, my professor prefers that we use a Makefile. I am just learning how to use Makefile and make, and I'm having trouble creating the Makefile. So far, this is what I have:
# RULES
EXEC := fftw_ex
SRC := $(wildcard *.c)
OBJ := $(patsubst %.c,%.o,%(SRC))
# OPERATIONS
CC := gcc
CFLAGS := -O3 -I$TACC_FFTW3_INC
LDFLAGS := -L$TACC_FFTW3_LIB
LDLIBS := -lfftw3
$(EXEC): $(OBJ)
$(CC) $(LDFLAGS) $(LDLIBS) -o -g $# $^
%.o: %.c
$(CC) $(CFLAGS) -c $<
# PHONY TARGETS
.PHONY: clean
clean:
#echo Cleaning...;rm -rf *.o fftw_ex
I know there's a problem with the SRC line, as i'm getting the error message:
make: *** No rule to make target `%(SRC)', needed by `fftw_ex'. Stop.
Any help to get this to work would be appreciated.
1)To resolve:
No rule to make target `%(SRC)'
replace %(SRC) in
OBJ := $(patsubst %.c,%.o,%(SRC))
with $(SRC)
2)In line:
$(CC) $(LDFLAGS) $(LDLIBS) -o -g $# $^
you have mistake: -o -g, should be -g -o