Makefile for linking opencv.framework (I'm not using cmake) - c++

I use opencv in my project, and now I compile the project into a static library using makefile, but always output 'fatal error: 'cv.h' file not found'. I have searched this site and elsewhere, it's not what I need. I only know a little makefile syntax. What should I do?
Makefile
LIBS_DIR = ./lib/
OBJS_DIR = ./obj/
DEPENDENT_DIR = ./dependent/
HEADER_PATH = -I./include -I./implement -I.
LIB_PATH = -L./lib
SRCDIRS := $(patsubst ./%, %, $(shell find . -type d))
SRCS_CXX := $(foreach dir, $(SRCDIRS), $(wildcard $(addprefix $(dir)\/*, .cpp)))
OBJS := $(SRCS_CXX:.cpp=.o)
%.o: %.cpp
#echo "---------- .o begin ----------"
$(CXX) -c $< $(HEADER_PATH)
$(CXX) -o $# $^ $(LIB_PATH)
mv $# $(OBJS_DIR)
%.d: %.cpp
#echo "---------- dependent begin ----------"
#set -e; \
rm -f $#; \
$(CXX) -MM $< > $#.tmp; \
sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.tmp > $#; \
rm -f $#.tmp
mv $# $(DEPENDENT_DIR)
-include $(DEPS)
.PHONY: clean
clean:
rm -f obj/*.o lib/*.a dependent/*.d
rm -rf SunWS_cache
In my file
#include <cv.h>
#include <cxcore.h>
#include <highgui.h>
File directory
Used makefile
New error
I modified the HEADER_PATH like HEADER_PATH = -I./include/opencv -I./include/opencv2 -I./implement -I. but a new error appeared, fatal error: 'opencv2/core/core_c.h' file not found.
I try to add a new subfolder path like -I./include/opencv -I./include/opencv2 -I./include/opencv2/core -I./implement -I. this error is still being output, -I command doesn't automatically find the path to the subfolder? am I doing anything wrong?

Your header paths are HEADER_PATH = -I./include -I./implement -I.
Inside the include folder you show in the attachment you have 2 subfolders opencv and opencv2.
When including the cv.h file is included directly without the subfolders.
For the compiler to find the files you either need to add the subfolders on the HEADER_PATH like HEADER_PATH = -I./include/opencv -I./include/opencv2 -I./implement
or you need to #include <opencv/cv.h>, that if cv.h is directly inside the opencv subfolder.
Side note: you have a typo in the folder denpendent

Finally, I solved this error and compiled successfully, I still use CMake. but after I successfully compiled with CMake, I can use the Makefile again to compile. I think it was my own mistake, #zomeck's answer helped me.
This is my CMakeLists.txt
cmake_minimum_required(VERSION 3.2)
project(library_name)
add_definitions(-Wall)
set(OPENCV_PATH ../sdk3/opencv3.0.0)
set(OPENCL_PATH ../sdk3/opencl)
link_directories(
${OPENCL_PATH}/bin
${OPENCV_PATH}
)
link_libraries(
${OPENCV_PATH}/opencv2.framework
${OPENCL_PATH}/bin/OpenCL.DLL
)
include_directories(
./
./implement
${OPENCV_PATH}/include
${OPENCV_PATH}/include/opencv
${OPENCL_PATH}/include/CL
)
set(SOURCES_FILES
HS_Process.cpp
implement/iclear/H_Proc.cpp
)
add_library(library_name STATIC ${SOURCES_FILES})
target_link_libraries(library_name opencv2 OpenCL)
New Makefile after #zomeck's answer
# The following is modified
SDK_PATH = ../sdk3
OPENCL_PATH = ../sdk3/opencl
OPENCV_PATH = ../sdk3/opencv3.0.0/include
vpath = %.h implement : %.h $(OPENCV_PATH) : %.h $(OPENCV_PATH)/opencv : %.h $(OPENCL_PATH) : %.h $(CALCTIME_PATH)
HEADER_PATH = \
-I. \
-I./implement \
-I$(OPENCV_PATH) \
-I$(OPENCV_PATH)/opencv \
-I$(OPENCV_PATH)/opencv2 \
-I$(OPENCL_PATH)/include/CL \
%.o: %.cpp
#echo "---------- .o begin ----------"
$(CXX) $(CXXFLAGS) -c $(HEADER_PATH) $< -o $#
mv $# $(OBJS_DIR)

Related

Makefile to compile a list of sources to custom directory

I have this makefile:
IDIR = include
SDIR = src
ODIR = obj
BDIR = build
DEPS = $(shell find $(IDIR)/ -name '*.hpp')
SRCS = $(shell find $(SDIR)/ -name '*.cpp')
OBJS = $(patsubst %.cpp,$(ODIR)/%.o,$(notdir $(SRCS)))
BIN = main
CPPC = g++
CFLAGS = -Wall -c
all: dir $(BDIR)/$(BIN)
#echo Finished compiling $(BIN)
dir:
mkdir -p $(BDIR)
mkdir -p $(ODIR)
$(BDIR)/$(BIN): $(OBJS)
$(CPPC) $^ -o $#
$(OBJS): $(SRCS)
$(CPPC) $(CFLAGS) $^ -o $#
clean:
rm -rf $(BDIR) $(ODIR)
When I try to make, I get the following error:
mkdir -p build
mkdir -p obj
g++ -Wall -c src/sdk/tcp/Tcp.cpp src/sdk/socket/Socket.cpp src/Main.cpp -o obj/Tcp.o
g++: fatal error: cannot specify ‘-o’ with ‘-c’, ‘-S’ or ‘-E’ with multiple files
compilation terminated.
make: *** [Makefile:27: obj/Tcp.o] Error 1
My question is, is it possible to achieve what I am trying with this makefile? Going through each source file in $(SRCS), and compile the object file directly inside the obj directory with just the basename. An example of obj directory after a successful compilation:
obj
/ | \
/ | \
Tcp.o Socket.o Main.o
Your $(OBJS) rule is wrong.
There are (at least) two ways to do this.
You could write a pattern rule and use vpath to locate the sources:
vpath %.cpp $(dir $(SRCS))
$(OBJS): obj/%.o: %.cpp
$(CPPC) $(CFLAGS) $^ -o $#
Or you could generate a rule for each object:
define template
$(patsubst %,obj/%.o,$(notdir $(1))): $(addsuffix .cpp,$(1))
echo $(CPPC) $(CFLAGS) $$^ -o $$#
endef
$(foreach src,$(SRCS),$(eval $(call template,$(basename $(src)))))

Make won't recompile header file changes. Despite including .d dependency files

I have a really strange issue with the Makefile in one of my off-time projects.
I have a Makefile (shown below) that generates dependency information in .d files following https://www.gnu.org/software/make/manual/html_node/Automatic-Prerequisites.html.
The problem is that a change in one of my header files (shader.h) does not trigger the recompilation of shader.o (out of shader.cpp).
The problem started happening recently when I re-organized the directory structure in my project so I suspect it is related to that.
The strange thing is that if I do make --print-data-base it does seem like it has found the correct prerequisites matching the shader.d file.
The diretory structure is as follows:
|-src
|-engine
|-shader.h
|-shader.cpp
|-bin
|-Debug
|-OpenGLTest
|-obj
|-Debug
|-engine
|-shader.o
|-dep
|-engine
|-shader.d
Makefile:
WORKDIR = `pwd`
CC = gcc
CXX = g++
AR = ar
LD = g++
WINDRES = windres
INC = -I/usr/local/include
CFLAGS = -Wall -Werror
CXX_FLAGS = -std=c++11
RESINC =
LIBDIR = -L/usr/local/lib
LIB = -lSDL2 -lGLEW -framework OpenGL
LDFLAGS =
DEPDIR = dep
SRCDIR = src
INC_DEBUG = $(INC)
CFLAGS_DEBUG = $(CFLAGS) -g
RESINC_DEBUG = $(RESINC)
RCFLAGS_DEBUG = $(RCFLAGS)
LIBDIR_DEBUG = $(LIBDIR)
LIB_DEBUG = $(LIB)
LDFLAGS_DEBUG = $(LDFLAGS)
OBJDIR_DEBUG = obj/Debug
DEP_DEBUG =
OUT_DEBUG = bin/Debug/OpenGLTest
CXX_SRCS = $(wildcard $(SRCDIR)/*.cpp) $(wildcard $(SRCDIR)/**/*.cpp)
CXX_REL_SRCS = $(subst $(SRCDIR)/,,$(CXX_SRCS))
OBJS = $(CXX_REL_SRCS:%.cpp=%.o)
OBJ_DEBUG = $(addprefix $(OBJDIR_DEBUG)/,$(OBJS))
# ----------------------------- debug -----------------------------
clean: clean_debug clean_release
rm -rf $(DEPDIR)
before_debug:
#test -d bin/Debug || mkdir -p bin/Debug
#test -d $(OBJDIR_DEBUG) || mkdir -p $(OBJDIR_DEBUG)
#mkdir -p $(dir $(OBJ_DEBUG))
after_debug:
debug: before_debug out_debug after_debug
out_debug: before_debug $(OBJ_DEBUG) $(DEP_DEBUG)
$(LD) $(LIBDIR_DEBUG) -o $(OUT_DEBUG) $(OBJ_DEBUG) $(LDFLAGS_DEBUG) $(LIB_DEBUG)
$(OBJDIR_DEBUG)/%.o: $(SRCDIR)/%.cpp
$(CXX) $(CFLAGS_DEBUG) $(CXX_FLAGS) $(INC_DEBUG) -c $< -o $#
clean_debug:
rm -f $(OBJ_DEBUG) $(OUT_DEBUG)
rm -rf bin/Debug
rm -rf $(OBJDIR_DEBUG)
# ----------------------------- dependencies -----------------------------
# Generate dependencies in *.d files
$(DEPDIR)/%.d: $(SRCDIR)/%.cpp
#test -d $(DEPDIR) || mkdir -p $(DEPDIR)
#mkdir -p $(dir $#)
#set -e; rm -f $#; \
$(CXX) -MM $(CFLAGS) $(CXX_FLAGS) $(INC) $< > $#.$$$$; \
sed 's,\(.*\)\.o[ :]*,$(OBJDIR_RELEASE)/\1.o $(OBJDIR_DEBUG)/\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
# Include the *.d files
include $(patsubst %,$(DEPDIR)/%.d,$(basename $(CXX_REL_SRCS)))
# ----------------------------- targets -----------------------------
.PHONY: before_debug after_debug clean_debug
all: debug
shader.d:
obj/Debug/shader.o dep/engine/shader.d : src/engine/shader.cpp src/engine/shader.h \
src/engine/transform.h src/engine/camera.h src/engine/constants.h
I'll answer this since the issue has been found by #G.M. in the comments.
Turns out that the dependency generation was flawed.
In shader.d obj/Debug/shader.o should really be obj/Debug/engine/shader.o. Modifying the sed command as shown below fixes this.
sed 's,\(.*\)\.o[ :]*,$(OBJDIR_RELEASE)/$(subst $(SRCDIR)/,,$(dir $<))\1.o $(OBJDIR_DEBUG)/$(subst $(SRCDIR)/,,$(dir $<))\1.o $# : ,g' < $#.$$$$ > $#;

C++ Make file issue "No rule to make target ..."

I just started working with makefile.
I am getting the error with makefile of my C++ project.
make: No rule to make target 'bin/smartCart_app', needed by all.
Below is the directory structure and files associated with it.
VBOX:~BASE$ls
build src
VBOX:~BASE$cd build
VBOX:~BASE/build$ ls
bin build Makefile.sc
VBOX:~BASE/build$ cd ../src
VBOX:~BASE/src$ls
baseStation.cpp config util //config and util has header and cpp files
Here is my Make file
CC=gcc
CPP=g++
CCFLAGS=-g -Wall -std=gnu+0x -o0
CC_LDFLAGS = -g -Wl
BUILD=./build
BIN = ./bin
SC_SRC_ROOT = ../src
SC_SRC_SUBDIRS = config util
SC_SRC_RELDIRS = $(addprefix $(strip $(SC_SRC_ROOT)), $(strip $(SC_SRC_SUBDIRS)))
SC_SRCS_ = $(shell /usr/bin/find $(SC_SRC_ROOT)/config $(SC_SRC_ROOT)/util -name "*.cpp")
SC_SRCS = $(SC_SRCS_) baseStation.cpp
SC_NEW_SRCS = $(notdir $(SC_SRCS))
SPACE :=
SPACE +=
INCLUDE = $(addprefix -I, $(SRC_RELDIRS))
VPATH = $(subst $(SPACE),:,$(SRC_RELDIRS)) $(subst $(SPACE),:,$(SC_SRC_RELDIRS))
SC_INCLUDE = $(addprefix -I, $(SC_SRC_RELDIRS))
SC_OBJS = $(SC_NEW_SRCS:%.cpp=$(BUILD)/%.o)
SC_DEPS = $(SC_OBJS:%.o=%.d)
# Ensure paths exist.
$(shell [ -d "$(BIN)" ] || mkdir -p $(BIN))
$(shell [ -d "$(BUILD)" ] || mkdir -p $(BUILD))
# Explicit rules.
.PHONY: all clean $(PHONY)
all: $(BIN)/smartCart_app
clean:
#echo "Cleaning..."
-#rm -f $(BIN)/smartCart_app $(SC_OBJS)
$(SC_OBJS): $(BUILD)/%.o: %.cpp
#echo "Compiling $(notdir $<)"
#$(CPP) $(CCFLAGS) $(INCLUDE) $(SC_INCLUDE) -MD -c -o $# $<
$(MACRO_DEPS):
-#rm -f $(patsubst %_ON.d,%_OFF.d,$#) $(patsubst %_OFF.d,%_ON.d,$#) $#
#touch $#
#$(ALL_OBJS): %.o: %.d
$(DEPS): $(BUILD)/%.d: %.cpp
#$(CC) $< -MM -MF $# $(INCLUDE)

How to write make files with auto dependancy generator

In expansion to my previous question how to write a makefile for structured file system:
The file structure:
.
├── Headers
│   ├── function.h
│   └── test.h
├── makefile
├── README.md
└── Sources
├── function.c
├── main.c
└── test.c
I'm trying to write a makefile that reads the #include<...> on any given source file and compile as required.
Originally I used to have a make file that looked like this:
INC_DIR = Headers
SRC_DIR = Sources
OBJ_DIR = Objects
#CXXFLAGS = -c -Wall -I. -IHeaders
CXXFLAGS = -c -Wall -I. -IHeaders
CC = gcc
SRCS = $(SRC_DIR)/*.c
OBJS = $(OBJ_DIR)/*.o
#The wildcard and patsubt commads will come handy
DEPS = $(INC_DIR)/*.h
#need to use an automatic dependency generator
output: $(OBJ_DIR)/main.o $(OBJ_DIR)/function.o
$(CC) $^ -o $#
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c $(DEPS)
$(CC) $(CXXFLAGS) $< -o $#
run: output
./output
clean:
rm $(OBJ_DIR)/*.o
rm output
-#echo "Clean completed"
That meant that for every source file that output was dependent on i had to add that object to this line.
output: $(OBJ_DIR)/main.o $(OBJ_DIR)/function.o $(OBJ_DIR)/test.o
$(CC) $^ -o $#
And is any other source file was dependent on one or more sources additional rules had to be added.
To solve this:
here is what I have gathered from Auto-Dependency Generation and 4.14 Generating Prerequisites Automatically
As mentioned by the community members, I have a mixed understanding of dependency generation and how to make use of the files generated.
DEP_DIR = .d
$(shell mkdir -p $(DEP_DIR) >/dev/null)
DEPFLAGS = -MT $# -MMD -MP -MF $(DEP_DIR)/$*.Td
INC_DIR = Headers
SRC_DIR = Sources
OBJ_DIR = Objects
$(shell mkdir -p $(OBJ_DIR) >/dev/null)
CXXFLAGS = -c -Wall -I. -IHeaders
CC = gcc
SRCS = $(SRC_DIR)/*.c
OBJS = $(OBJ_DIR)/*.o
#The wildcard and patsubt commads will come handy
#DEPS = $(INC_DIR)/*.h
MAKEDEPEND = $(CC) $(CXXFLAGS) $< \
| sed -n 's/^\# *[0-9][0-9]* *"\([^"]*\)".*/$*.o: \1/p' \
| sort | uniq > $*.Td
COMPILE.c = $(CC) $(DEPFLAGS) $(CXXFLAGS)
#need to use an automatic dependency generator
#%.d: %.c
# #set -e; rm -f $#; \
# $(CC) -MP -MD $(CXXFLAGS) $< > $#.$$$$; \
# sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
# rm -f $#.$$$$
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c $(DEP_DIR)/%.d
#$(MAKEDEPEND); \
cp $*.Td $*.d; \
sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
-e '/^$$/ d' -e 's/$$/ :/' < $*.Td >> $*.d; \
rm -f $*.Td
#$(COMPILE.c) -o $# $<
$(CC) $(CXXFLAGS) $(DEPFLAGS) $< -o $#
-include $(SRCS:.c=.d)
$(DEP_DIR)/%.d: ;
.PRECIOUS: $(DEP_DIR)/%.d
output: $(OBJS)
$(CC) $^ -o $#
run: output
./output
clean:
rm -r $(OBJ_DIR)
rm -r $(DEP_DIR)
rm output
-#echo "Clean completed"
The error when make is executed is:
$ make
gcc -c -Wall -I. -IHeaders -MT Objects/*.o -MMD -MP -MF .d/*.Td Sources/function.c -o Objects/*.o
gcc Objects/*.o -o output
/usr/lib/gcc/x86_64-linux-gnu/5/../../../x86_64-linux-gnu/crt1.o: In function `_start':
(.text+0x20): undefined reference to `main'
collect2: error: ld returned 1 exit status
makefile:48: recipe for target 'output' failed
make: *** [output] Error 1
So, I'm hoping to achieve the auto dependency detection and compilation. I think the error is in the way that the dependencies are detected and the way they are generated for a given source file.
It looks to me like you're trying to combine multiple different ways of generating dependency info, and that can't work. The advanced post talks about multiple ways to solve the problem: you need to pick one not try to use them all together.
If you want to use the advanced method then use it as described in the "TL;DR" section at the top, or else in the "Combining Compilation and Dependency Generation" section at the bottom. If you're using GCC there's no need for MAKEDEPEND, sed, etc.
The advanced post says that your rule should look like this:
COMPILE.c = $(CC) $(DEPFLAGS) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
POSTCOMPILE = mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d
%.o : %.c
%.o : %.c $(DEPDIR)/%.d
$(COMPILE.c) $(OUTPUT_OPTION) $<
$(POSTCOMPILE)
That's it.

-I flag in the makefile does not result in a header file being found (gtest/gtest.h)

Previously I was struggling with creating a makefile in root directory that would deal with source files being in src folder and headers in include folder. Following this I wanted to add another folder tests where I would keep .cpp files with tests. Unfortunately I have problems with this.
The folder structure is:
.
|__makefile
|
|__/src
| |
| |__[regular .cpp files]
|
|__/include
| |
| |__[.h files]
| |
| |__/gtest
| |
| |__gtest.h
|
|__/tests
|
|__test_factorial.cpp
./tests/test_factorial.cpp:
#include "gtest/gtest.h"
#include "factorial.h"
// some tests
makefile:
CC = g++
CFLAGS = -Wall
INCLUDES = -I./include
LIBS = -lgtest -lpthread
SOURCEDIR = ./src/
SRCS = $(shell find ./src/ -name '*.cpp')
SRCS += $(shell find ./tests/ -name '*.cpp')
.PHONY: clean depend
SRCS := $(filter-out ./tests/main_tests.cpp, $(SRCS))
OBJS = $(SRCS:.cpp=.o)
OBJS := $(OBJS:./src%=.%)
release: $(OBJS)
$(CC) $(CFLAGS) -o app $(OBJS) $(LIBS)
VPATH = ./src:./tests
%.o: ./src/%.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c ./src/$*.cpp
%.o: ./tests/%.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c ./tests/$*.cpp
depend: .depend
.depend: $(SRCS)
rm -f ./.depend
$(CC) $(CFLAGS) $(INCLUDES) -MM $^ > ./.depend;
include .depend
When I execute make from the root directory all the files from /src compile fine (I end up having object files in the root directory for them) but I get an error for .cpp file from /tests directory:
g++ -c -o tests/test_factorial.o tests/test_factorial.cpp
tests/test_factorial.cpp:1:25: fatal error: gtest/gtest.h: No such file or directory
compilation terminated.
<builtin>: recipe for target 'tests/test_factorial.o' failed
make: *** [tests/test_factorial.o] Error 1
What might be important, the .depend file seems to have it all right:
test_factorial.o: tests/test_factorial.cpp include/gtest/gtest.h \
include/factorial.h
What is wrong with the makefile?
EDIT
I believe this fragment of the error:
<builtin>: recipe for target 'tests/test_factorial.o' failed
suggests that something is wrong in this part of the makefile:
%.o: ./src/%.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c ./src/$*.cpp
%.o: ./tests/%.cpp
$(CC) $(CFLAGS) $(INCLUDES) -c ./tests/$*.cpp
Why it's trying to do ./tests/test_factorial.o rather than ./test_factorial.o? Let me underline again that object files for ./src/*.cpp files end up in root directory, i.e. ./*.o, not ./src/*.o.
Your makefile is building
tests/test_factorial.o
from
tests/test_factorial.cpp
and that doesn't match the rule
%.o: ./tests/%.cpp
So it is instead using a builtin rule. (As an aside, the convention is to build c++ files using $(CXX) and $(CXXFLAGS) not $(CC)).
Try a rule pattern of
./tests/%.o: ./tests/%.cpp
The reason that your Makefile uses the name tests/test_factorial.o is because
OBJS = $(SRCS:.cpp=.o)
which (it should be obvious) makes the path to the .o file the same as the path to the .cpp.
You have a subsequent rule stripping the path src/
OBJS := $(OBJS:./src%=.%)
and no similar rule for tests/