linux C++ gmake "No rule to make target" - c++

It's been a couple decades since I've had to manage makefiles. I've checked existing answers here, as well as googling elsewhere. When I use the target: $(BIN)/$(EXECUTABLE): $(OBJECTS)
I'm stumped as to why my makefile is failing with:
$ make
make: *** No rule to make target 'src/SRecord.o', needed by 'bin/main'. Stop.
Here's the Makefile:
# execute `make D='-g'` to make with debug symbols
DEFS := $(D)
CC := gcc $(DEFS)
CFLAGS := -std=c99 -Wall -Wextra
CXX := g++ $(DEFS)
CXXFLAGS := -std=c++17 -Wall -Wextra
BIN := bin
SRC := src
INCLUDE := include
LIB := lib
#LIBSOURCES := $(wildcard $(LIB)/*.cpp)
#LIBOBJECTS := $(LIBSOURCES:%.cpp=%.o)
#OBJECTS := $(subst $(LIB)/,,$(LIBOBJECTS))
SOURCES := $(wildcard $(SRC)/*.cpp)
OBJECTS := $(SOURCES:%.cpp=%.o)
# SOURCES := \
# $(SRC)/main.cpp \
# $(SRC)/SerialPort.cpp \
# $(SRC)/ShadowUpdate.cpp \
# $(SRC)/SRecord.cpp
# OBJECTS := \
# $(SRC)/SerialPort.o \
# $(SRC)/ShadowUpdate.o \
# $(SRC)/SRecord.o
EXECUTABLE := main
#
# Targets
#
.PHONY: clean all
all: $(BIN)/$(EXECUTABLE)
clean:
$(RM) $(BIN)/$(EXECUTABLE)
$(RM) $(OBJECTS)
run: all
./$(BIN)/$(EXECUTABLE)
# $(BIN)/$(EXECUTABLE): $(SRC)/*
$(BIN)/$(EXECUTABLE): $(OBJECTS)
$(CXX) $(CXXFLAGS) -I$(INCLUDE) -L$(LIB) $^ -o $#
#
# Dependencies - must be at end of makefile
#
DEPDIR := .d
$(shell mkdir -p $(DEPDIR) >/dev/null)
DEPFLAGS = -MT $# -MMD -MP -MF $(DEPDIR)/$*.Td
POSTCOMPILE = #mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d && touch $#
%.o: %.c
%.o: %.c $(DEPDIR)/%.d
$(CC) -c -o $*.o $(DEPFLAGS) $(CFLAGS) $<
$(POSTCOMPILE)
%.o: %.cpp
%.o: %.cpp $(DEPDIR)/%.d
$(CXX) -c -o $*.o $(DEPFLAGS) $(CXXFLAGS) $<
$(POSTCOMPILE)
$(DEPDIR)/%.d: ;
.PRECIOUS: $(DEPDIR)/%.d
include $(wildcard $(patsubst %,$(DEPDIR)/%.d,$(basename $(SOURCES))))
It works with the commented out target: # $(BIN)/$(EXECUTABLE): $(SRC)/*
But, I want to be able to have a more complex project than simply listing all the source files as dependencies to the executable.
Here's my file tree:
src/
src/SerialPort.cpp
src/SRecord.cpp
src/ShadowUpdate.cpp
src/main.cpp
include
include/ShadowUpdate.h
include/SerialPort.h
include/SRecord.h
include/the_exo.h
bin/
bin/main
Makefile
lib/
.d/
The automatic dependency generation isn't working either, even though it is straight from GNU's website.

Think about what the % expands to in
%.o: %.cpp $(DEPDIR)/%.d
plugging in src/SRecord.o:
src/SRecord.o: src/SRecord.cpp .d/src/SRecord.d
Can you see the issue? Try the following instead
$(SRC)/%.o: $(SRC)/%.cpp $(SRC)/$(DEPDIR)/%.d
You won't need the lines that override the built-in recipes (%.o: %.cpp), get rid of them.

For clarity to anyone looking for the answer in the future, I'm posting my revised Makefile:
BIN := bin
SRC := src
INCLUDE := include
LIB := lib
# execute `make D='-g'` to make with debug symbols
DEFS := $(D)
CC := gcc $(DEFS)
CFLAGS := -I$(INCLUDE) -std=c99 -Wall -Wextra
CXX := g++ $(DEFS)
CXXFLAGS := -I$(INCLUDE) -std=c++17 -Wall -Wextra
#LIBSOURCES := $(wildcard $(LIB)/*.cpp)
#LIBOBJECTS := $(LIBSOURCES:%.cpp=%.o)
#OBJECTS := $(subst $(LIB)/,,$(LIBOBJECTS))
SOURCES := $(wildcard $(SRC)/*.cpp)
OBJECTS := $(SOURCES:%.cpp=%.o)
EXECUTABLE := main
#
# Targets
#
.PHONY: clean all
all: $(BIN)/$(EXECUTABLE)
clean:
$(RM) $(BIN)/$(EXECUTABLE)
$(RM) $(OBJECTS)
run: all
./$(BIN)/$(EXECUTABLE)
$(BIN)/$(EXECUTABLE): $(OBJECTS)
$(CXX) $(CXXFLAGS) -L$(LIB) $^ -o $#
#
# Dependencies - must be at end of makefile
#
DEPDIR := $(SRC)/.d
$(shell mkdir -p $(DEPDIR) >/dev/null)
DEPFLAGS = -MT $# -MMD -MP -MF $(DEPDIR)/$*.Td
POSTCOMPILE = #mv -f $(DEPDIR)/$*.Td $(DEPDIR)/$*.d && touch $#
%.o: %.c
%.o: %.c $(DEPDIR)/%.d
$(CC) -c -o $# $(DEPFLAGS) $(CFLAGS) $<
$(POSTCOMPILE)
%.o: %.cpp
$(SRC)/%.o: $(SRC)/%.cpp $(DEPDIR)/%.d
$(CXX) -c -o $# $(DEPFLAGS) $(CXXFLAGS) $<
$(POSTCOMPILE)
$(DEPDIR)/%.d: ;
.PRECIOUS: $(DEPDIR)/%.d
include $(wildcard $(patsubst %,$(DEPDIR)/%.d,$(basename $(SOURCES))))
To clarify my comment to the above answer, if I comment out the "override" target (%.o: %.cpp), here's the output:
$ make clean; make
rm -f bin/main
rm -f src/SRecord.o src/SerialPort.o src/ShadowUpdate.o src/main.o
g++ -Iinclude -std=c++17 -Wall -Wextra -c -o src/SRecord.o src/SRecord.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -c -o src/SerialPort.o src/SerialPort.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -c -o src/ShadowUpdate.o src/ShadowUpdate.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -c -o src/main.o src/main.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -Llib src/SRecord.o src/SerialPort.o src/ShadowUpdate.o src/main.o -o bin/main
Clearly, the dependencies are not being made. My rule was not executed.
But, with the empty %.o: %.cpp target in place, the make performs as expected:
$ make clean; make
rm -f bin/main
rm -f src/SRecord.o src/SerialPort.o src/ShadowUpdate.o src/main.o
g++ -c -o src/SRecord.o -MT src/SRecord.o -MMD -MP -MF src/.d/SRecord.Td -Iinclude -std=c++17 -Wall -Wextra src/SRecord.cpp
g++ -c -o src/SerialPort.o -MT src/SerialPort.o -MMD -MP -MF src/.d/SerialPort.Td -Iinclude -std=c++17 -Wall -Wextra src/SerialPort.cpp
g++ -c -o src/ShadowUpdate.o -MT src/ShadowUpdate.o -MMD -MP -MF src/.d/ShadowUpdate.Td -Iinclude -std=c++17 -Wall -Wextra src/ShadowUpdate.cpp
g++ -c -o src/main.o -MT src/main.o -MMD -MP -MF src/.d/main.Td -Iinclude -std=c++17 -Wall -Wextra src/main.cpp
g++ -Iinclude -std=c++17 -Wall -Wextra -Llib src/SRecord.o src/SerialPort.o src/ShadowUpdate.o src/main.o -o bin/main

Related

Im working on a makefile which should build a library and then also include that library when building the entire program

INC_DIR = ./include
SRC_DIR = ./src
OBJ_DIR = ./obj
SRC_FILES = $(wildcard $(SRC_DIR)/*.cpp))
H_FILES = $(wildcard $(INC_DIR)/*.cpp)
OBJ_FILES=$(patsubst $(SRC_DIR)/%.cc,$(OBJ_DIR)/%.o,$(SRC_FILES)
TARGET = PT3
CC = g++
CFLAGS = - fPIC -c -Wall -Werror -pedantic -std=c++11 -Wno-c++11-extensions
CPPFLAGS = $(addprefix -I, $(INC_DIR))
clean:
rm -f $(OBJECTS) $(TARGET)
all: $(TARGET)
$(TARGET): $(OBJECTS)
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# $^
%.o: %.cc
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# -c $<
g++ -shared -fPIC -o libtest.so $(OBJECTS)
main.o: main.cc
$(CC) $(CFLAGS) $(CPPFLAGS) -L/pt3/lib -o maintest main.cc -libtest
this is currently what I have and i know its not syntactically right or remotely working but Im getting stuck on creating the shared library so I dont even know what else wouldnt compile.**
INC_DIR = ./include
SRC_DIR = ./src
SRC_FILES = $(sort $(shell find $(SRC_DIR) -name '*.cc'))
OBJ_FILES = $(SRC_FILES:.cc=.o)
TARGET = PT3
CC = g++
CFLAGS = -fPIC -Wall -Werror -pedantic -std=c++11 -Wno-c++11-extensions
CPPFLAGS = $(addprefix -I, $(INC_DIR))
#clean:
# rm -f $(OBJECTS) $(TARGET)
all: $(TARGET)
$(TARGET): $(OBJ_FILES)
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# $^
%.o: %.cc
$(CC) $(CFLAGS) $(CPPFLAGS) -o $# -c $<
libtest.so: $(OBJ_FILES)
$(CC) -shared -fPIC -o $# $^
maintest: main.o libtest.so
$(CC) $(CFLAGS) $(CPPFLAGS) -L. -o maintest main.o -libtest
this is what i rewrote the code to however Im getting a no input files error, but Im not sure if thats coming from a wrong read / failure to get into the required folders, or due to possibly missing a -o or -c?
Ive worked on the code some more following the suggestions and have come to this:
CXX = g++
CXXFLAGS := -Wall -Werror -pedantic -std=c++11 -Wno-c++11-extensions
SRC_FILES = $(wildcard $(SRC_DIR)/*.cpp)
OBJECTS=$(patsubst $(SRC_DIR)/%.cpp,$(OBJ_DIR)/%.o,$(SRC_FILES))
INC_DIR = include
SRC_DIR = src
OBJ_DIR = obj
TEST_DIR = tests
LIB_DIR = lib
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(CXXFLAGS) -fPIC -Iinclude -o $# -c $<
clean:
rm -f $(OBJECTS) $(TEST_DIR)/main.o
$(LIB_DIR)/libtest.so: $(OBJECTS)
#echo frank
$(CXX) -shared -fPIC -o $# $^
$(TEST_DIR)/main.o: $(TEST_DIR)/main.cc
$(CXX) $(CXXFLAGS) -Iinclude -o $# -c $<
maintest: $(TEST_DIR)/main.o $(LIB_DIR)/libtest.so
$(CXX) $(CXXFLAGS) -Llib -Iinclude -o $# $< -ltest
everything seems to compile fine however when running the maintest program it returns an error saying: error while loading shared libraries: libtest.so: cannot open shared object file: No such file or directory
thanks for the suggestions so far I feel like Im on the verge of actually getting the makefile working as intended
You've already written the recipe for the library (which builds it in the working directory -- we can change that later if you want):
g++ -shared -fPIC -o libtest.so $(OBJECTS)
The next step is to put it into a rule:
libtest.so: $(OBJECTS)
g++ -shared -fPIC -o libtest.so $(OBJECTS)
Then clean it up:
libtest.so: $(OBJECTS)
g++ -shared -fPIC -o $# $^
It looks as if you want the executable to be maintest, so let's write a rule for that:
maintest: main.o libtest.so
$(CC) $(CFLAGS) $(CPPFLAGS) -L. -o maintest main.o -ltest
Give that a try. We can make further adjustments once that much works.
EDIT: I see that there are a few other problems in your makefile. Your variables won't work as written. Do you name your source files "foo.cc" or "foo.cpp"?
EDIT: I can see that we'll have to do this in stages.
Step 1. Try this:
CXX = g++
CXXFLAGS := -Wall -Werror -pedantic -std=c++11 -Wno-c++11-extensions
INC_DIR = include
SRC_DIR = src
OBJ_DIR = obj
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CXX) $(CXXFLAGS) -Iinclude -o $# -c $<
Try to build one or two object files with this, as in make obj/foo.o.
Step 2. Add a rule for main.o, and test it:
$(OBJ_DIR)/main.o: main.cc
$(CXX) $(CXXFLAGS) -Iinclude -o $# -c $<
Step 3. Add a "do nothing" rule for the library, and verify that it builds all of the objects:
SRC_FILES = $(wildcard $(SRC_DIR)/*.cpp)
OBJECTS=$(patsubst $(SRC_DIR)/%.cpp,$(OBJ_DIR)/%.o,$(SRC_FILES))
libtest.so: $(OBJECTS)
#echo doing nothing
Step 4. Change the library rule to actually build the library:
libtest.so: $(OBJECTS)
$(CXX) -shared -fPIC -o $# $^
Step 5. Add a rule to build the test:
maintest: main.o libtest.so
$(CXX) $(CXXFLAGS) -L. -o $# $< -ltest

C++ Makefile. .o in different subdirectories

I have some problems trying to put .o files into a separate directory (/build).
Actually, my sources (in /src) contain some subdirectories, and my Makefile only create the .o of the .cpp contained at the first "level". The other .o are just ignored, so, the target cannot be created.
In my /src directory, I have "three levels" (src/first/second/).
Here's the code of the Makefile :
CC=g++
CFLAGS=-W -Wall -ansi -pedantic -s -O3 -Os -std=c++11 -fpermissive
LDFLAGS= -lboost_system -lboost_regex
SRCDIR=src
HEADDIR=include
LIBDIR=build
BINDIR=bin
BIN=LTN
SRC = $(wildcard src/*.cpp src/*/*.cpp src/*/*/*.cpp)
OBJ = $(patsubst %.cpp,$(LIBDIR)/%.o,$(SRC))
all: $(BIN)
LTN: $(OBJ)
$(CC) -o $(BINDIR)/$# $^ $(LDFLAGS)
$(LIBDIR)/$(SRCDIR)/%.o: $(SRCDIR)/%.cpp $(HEADDIR)/%.h
$(CC) -o $# -c $< $(CFLAGS)
.PHONY = clean
You can try this:
CC=g++
CFLAGS=-W -Wall -ansi -pedantic -s -O3 -Os -std=c++11 -fpermissive
LDFLAGS= -lboost_system -lboost_regex
SRCDIR=src
HEADDIR=include
LIBDIR=build
BINDIR=bin
BIN=LTN
SRC=$(shell find . -name '*.cpp')
TMP=$(subst $(SRCDIR),$(LIBDIR), $(SRC))
OBJ=$(patsubst %.cpp,%.o,$(TMP))
all: $(BIN)
LTN: $(OBJ)
#[ ! -d $(BINDIR) ] & mkdir -p $(BINDIR)
$(CC) -o $(BINDIR)/$# $^ $(LDFLAGS)
$(LIBDIR)/%.o: $(SRCDIR)/%.cpp
#[ ! -d $(dir $#) ] & mkdir -p $(dir $#)
$(CC) -o $# -c $< $(CFLAGS)
.PHONY = clean

Makefile for shared library that only compiles changed files?

I am working on a project where I am creating a .so object as my output that contains several operators for use in another program. I was given a Makefile that works just fine, except it always recompiles every file whenever I run make. Originally this was not an issue, but now that there are upwards of five or more operators in the library, running make is prohibitively slow. The trouble is that for the life of me, I can't figure out how to change this Makefile into one that behaves the way I want since I've never dealt with Makefiles in this format before:
BOOST_LOCATION=/usr/local/boost_1_54_0
CFLAGS=-pedantic -W -Wextra -Wall -Wno-strict-aliasing -Wno-long-long -Wno-unused-parameter -fPIC -D__STDC_FORMAT_MACROS -Wno-system-headers -isystem -O2 -g -DNDEBUG -ggdb3 -D__STDC_LIMIT_MACROS
INC=-I. -DPROJECT_ROOT="\"$(IN_SOURCE_DIR)\"" -I"$(IN_SOURCE_DIR)/include" -I"$(BOOST_LOCATION)"
LIBS=-L"$(IN_SOURCE_DIR)/lib" -shared -Wl,-soname,libname.so -L. -lm
all:
#if test ! -d "$(IN_SOURCE_DIR)"; then echo "Error. Try:\n\nmake IN_SOURCE_DIR=<PATH TO SOURCE TRUNK>"; exit 1; fi
$(CXX) $(CFLAGS) $(INC) -o plugin.cpp.o -c plugin.cpp
$(CXX) $(CFLAGS) $(INC) -o LogicalFile1.cpp.o -c File1/LogicalFile1.cpp
$(CXX) $(CFLAGS) $(INC) -o PhysicalFile1.cpp.o -c File1/PhysicalFile1.cpp
$(CXX) $(CFLAGS) $(INC) -o LogicalFile2.cpp.o -c File2/LogicalFile2.cpp
$(CXX) $(CFLAGS) $(INC) -o PhysicalFile2.cpp.o -c File2/PhysicalFile2.cpp
### etc.
$(CXX) $(CFLAGS) $(INC) -o libname.so \
plugin.cpp.o \
LogicalFile1.cpp.o \
PhysicalFile1.cpp.o \
LogicalFile2.cpp.o \
PhysicalFile2.cpp.o \
### etc \
$(LIBS)
clean:
rm -f *.o *.so
The biggest issue I have is that there is only one rule (all), and I cannot find an example of a Makefile that does this or how to split it into multiple rules.
In this case, it's actually pretty straightforward. Right now, you just have an all target that's doing all the building. You need to break out the compiler invocations and link step into their own rules, and you should be off to the races:
BOOST_LOCATION=/usr/local/boost_1_54_0
CFLAGS=-pedantic -W -Wextra -Wall -Wno-strict-aliasing -Wno-long-long -Wno-unused-parameter -fPIC -D__STDC_FORMAT_MACROS -Wno-system-headers -isystem -O2 -g -DNDEBUG -ggdb3 -D__STDC_LIMIT_MACROS
INC=-I. -DPROJECT_ROOT="\"$(IN_SOURCE_DIR)\"" -I"$(IN_SOURCE_DIR)/include" -I"$(BOOST_LOCATION)"
LIBS=-L"$(IN_SOURCE_DIR)/lib" -shared -Wl,-soname,libname.so -L. -lm
all: plugin.cpp.o LogicalFile1.cpp.o PhysicalFile1.cpp.o LogicalFile2.cpp.o PhysicalFile2.cpp.o
$(CXX) $(CFLAGS) $(INC) -o libname.so \
plugin.cpp.o \
LogicalFile1.cpp.o \
PhysicalFile1.cpp.o \
LogicalFile2.cpp.o \
PhysicalFile2.cpp.o \
### etc \
$(LIBS)
plugin.cpp.o: plugin.cpp | test
$(CXX) $(CFLAGS) $(INC) -o plugin.cpp.o -c plugin.cpp
LogicalFile1.cpp.o: File1/LogicalFile1.cpp | test
$(CXX) $(CFLAGS) $(INC) -o LogicalFile1.cpp.o -c File1/LogicalFile1.cpp
PhysicalFile1.cpp.o: File1/PhysicalFile1.cpp | test
$(CXX) $(CFLAGS) $(INC) -o PhysicalFile1.cpp.o -c File1/PhysicalFile1.cpp
LogicalFile2.cpp.o: File2/LogicalFile2.cpp | test
$(CXX) $(CFLAGS) $(INC) -o LogicalFile2.cpp.o -c File2/LogicalFile2.cpp
PhysicalFile2.cpp.o: File2/PhysicalFile2.cpp | test
$(CXX) $(CFLAGS) $(INC) -o PhysicalFile2.cpp.o -c File2/PhysicalFile2.cpp
test:
#if test ! -d "$(IN_SOURCE_DIR)"; then echo "Error. Try:\n\nmake IN_SOURCE_DIR=<PATH TO SOURCE TRUNK>"; exit 1; fi
clean:
rm -f *.o *.so
.PHONY: all clean test
From this point, you can simplify further, too. You could consolidate all of the compile lines into a single pattern rule, for example.
If you're willing to use the standard formats and built-in rules for make, you can write your entire makefile as easily as this:
ifeq (,$(wildcard $(IN_SOURCE_DIR)/.))
$(error Try: make IN_SOURCE_DIR=<PATH TO SOURCE TRUNK>)
endif
OBJECTS = plugin.o LogicalFile1.o PhysicalFile1.o LogicalFile2.o PhysicalFile2.o ### etc
BOOST_LOCATION = /usr/local/boost_1_54_0
CPPFLAGS = -DNDEBUG -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I. -DPROJECT_ROOT="\"$(IN_SOURCE_DIR)\"" -I"$(IN_SOURCE_DIR)/include" -I"$(BOOST_LOCATION)"
CXXFLAGS = -pedantic -W -Wextra -Wall -Wno-strict-aliasing -Wno-long-long -Wno-unused-parameter -fPIC -Wno-system-headers -isystem -O2 -g -ggdb3
LDFLAGS = -L"$(IN_SOURCE_DIR)/lib" -L.
LDLIBS = -shared -Wl,-soname,libname.so -lm
all: libname.so
libname.so: $(OBJECTS)
$(LINK.cc) $^ $(LDLIBS) -o $#
clean:
rm -f *.o *.so
.PHONY: all clean

creating a makefile for multiple targets

i have created a Makefile which i would change so, that it will generate more then one target when i run make.
In my program i use self predefined macros (e.g. TIME, REG and _DEBUG ) and i would like to have my Makefile i that way that it will generate one target with out predefined macros, one with REG and another one with REG and TIME.
I hope that what i wish is a reasonable wish from Makefile, if not, then please let me know.
P.S.:
recommendations would be gladly excepted
I am using
Here is my Makefile:
CXX = g++
SOURCES = random.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECUTABLE = random-64bit
DEBUG = -g -p -ggdb
CXXFLAGS = -Wall -ansi -pedantic -W -pipe -O3 -std=gnu++0x -march=native \
--fast-math -ftree-vectorize -ffast-math -D NDEBUG \
-D TIME -D REG -D _DEBUG
#CXXFLAGS+=$(DEBUG)
DEPS = def_type.hpp \
ls_regression.hpp \
network.hpp \
statistics.hpp \
knot.hpp \
nachbarn.hpp \
$(SOURCES:.cpp=.hpp) \
zufallszahlengenerator.hpp
INCLUDES = -I/home/phymihsa/eigen/ -I/home/phymihsa/boost_1_48_0
LIBPATH = -L/usr/local/lib64
LDFLAGS = -lm
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS) $(DEPS)
$(CXX) $(LIBPATH) $(OBJECTS) -o $#
.cpp.o: $<
$(CXX) $(LIBPATH) $(INCLUDES) $(LDFLAGS) $(CXXFLAGS) -c $<
%.o: %.cpp
$(CXX) $(LIBPATH) $(INCLUDES) $(LDFLAGS) $(CXXFLAGS) -c $<
.PHONY: clean
clean:
rm -rf $(OBJECTS) $(EXECUTABLE) *~ p1 *.o
EDIT
Based on the answer of #trojanfoe, i would to know if it is possible to use arrays
OBJECTS = $(SOURCES:.cpp=_none.o) $(SOURCES:.cpp=_reg.o) $(SOURCES:.cpp=_reg_time.o)
EXECUTABLE = $(SOURCES:.cpp=_none) $(SOURCES:.cpp=_reg) $(SOURCES:.cpp=_reg_time)
instead of each one writing each one specific?
Here is what i was searching for:
CXX = g++
OPTIONS := none reg reg_inter reg_time
none_CXXFLAGS :=
reg_CXXFLAGS := -D REG
reg_inter_CXXFLAGS := $(reg_CXXFLAGS) -D INTERMEDIATE_STEP
reg_time_CXXFLAGS := $(reg_CXXFLAGS) -D TIME
EXECUTABLES = $(addprefix random_,$(OPTIONS))
DEBUG = -g3 -p -ggdb
CXXFLAGS = -Wall -ansi -pedantic -W -pipe -O3 -std=gnu++0x -march=core2 -mtune=core2 \
--fast-math -ftree-vectorize -ffast-math -D NDEBUG
CXXFLAGS+=$(DEBUG)
DEPS = def_type.hpp \
ls_regression.hpp \
network.hpp \
statistics.hpp \
knot.hpp \
nachbarn.hpp \
zufallszahlengenerator.hpp
INCFLAGS = -I/usr/include/eigen3 -I/usr/include/boost_1_48
LIBPATH = -L/usr/lib64
LDFLAGS = -lm
.PHONY: all
all: $(EXECUTABLES)
random_%: random_%.o
$(CXX) $(LDFLAGS) $(LIBPATH) $^ -o $#
random_%.o : random.cpp $(DEPS)
$(CXX) $(INCFLAGS) $(CXXFLAGS) $($*_CXXFLAGS) -c $< -o $#
.PHONY: clean
clean:
rm -rf $(OBJECTS) $(EXECUTABLES) *~ p1 *.o
in this solution there is a use of variables instead of writing each time the all text
regards
You'll need to generate 3 different versions of the object file from random.cpp and 3 different executables. Note $(CXXFLAGS) contains flags common across all 3 targets and I've also moved $(DEPS) to be a dependency of the object files, not the executable.
CXX = g++
SOURCES = random.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECUTABLE = random-64bit
DEBUG = -g -p -ggdb
CXXFLAGS = -Wall -ansi -pedantic -W -pipe -O3 -std=gnu++0x -march=native \
--fast-math -ftree-vectorize -ffast-math -D NDEBUG -D _DEBUG
#CXXFLAGS+=$(DEBUG)
DEPS = def_type.hpp \
ls_regression.hpp \
network.hpp \
statistics.hpp \
knot.hpp \
nachbarn.hpp \
$(SOURCES:.cpp=.hpp) \
zufallszahlengenerator.hpp
INCLUDES = -I/home/phymihsa/eigen/ -I/home/phymihsa/boost_1_48_0
LIBPATH = -L/usr/local/lib64
LDFLAGS = -lm
all: random_none random_reg random_reg_time
random_none: random_none.o
$(CXX) $(LDFLAGS) $(LIBPATH) random_none.o -o $#
random_reg: random_reg.o
$(CXX) $(LDFLAGS) $(LIBPATH) random_reg.o -o $#
random_reg_time: random_reg_time.o
$(CXX) $(LDFLAGS) $(LIBPATH) random_reg_time.o -o $#
random_none.o: random.cpp $(DEPS)
$(CXX) $(INCLUDES) $(CXXFLAGS) -c $<
random_reg.o: random.cpp $(DEPS)
$(CXX) $(INCLUDES) $(CXXFLAGS) -D REG -c $<
random_reg_time.o: random.cpp $(DEPS)
$(CXX) $(INCLUDES) $(CXXFLAGS) -D REG -D TIME -c $<
.PHONY: clean
clean:
rm -rf *.o random_none random_reg random_reg_time *~ p1
For each file, create one target per compile flag variant.
Say you have a program that depends on two files, foo.cc and bar.cc. You want to compile a debug and a release version. You'll do something like this:
DEBUG = -g -Wall -D DEBUG
RELEASE = ...
foo_debug.o: foo.cc
g++ -o foo_debug.o -c foo.cc $(DEBUG)
foo_release.o: foo.cc
g++ -o foo_release.o -c foo.cc $(RELEASE)
# Same thing for bar ...
main_debug: foo_debug.o bar_debug.o
g++ -o main_debug foo_debug.o bar_debug.o
main_release: foo_release.o bar_release.o
g++ -o main_release foo_release.o bar_release.o

makefile to compile multiple sources, with different flags

I have the following makefile:
CC = gcc
SRC = source1.c
EXE = source1
FLAGS = -fopenmp
all: $(src)
$(CC) -o $(EXE) $(SRC) $(FLAGS)
clean:
rm $(EXE)
How can I modify it so I can use multiple sources, some of them compiled with the flag -fopenmp, some of them compiled without. Thanks a lot.
This should get you started: Note how -fopenmp gets added just for source2.c
CC=gcc
SRC=source1.c source2.c
OBJ=$(patsubst %.c,%.o,$(SRC))
EXE=source1
FLAGS= -g -O2
source2.o: FLAGS+=-fopenmp
all: $(EXE)
$(EXE): $(OBJ)
$(CC) -o $# $^ $(FLAGS)
%.o: %.c
$(CC) -c -o $# $^ $(FLAGS)
clean:
rm $(EXE)$
Output of make -Bsn:
gcc -o source1.o source1.c -g -O2
gcc -o source2.o source2.c -g -O2 -fopenmp
gcc -o source1 source1.o source2.o -g -O2
You can define for example, EXTFLAGS=$(FLAGS) -fopenmp, and use EXTFLAGS for some rules.