I'm trying to write my own makefile for a C++ program.
I'm editing an old makefile for a C program one of my teacher gave m, but I really don't understand why it keeps telling me that linking is not done.
I have 4 classes with their corresponding headers plus the main file.
This is my makefile:
OBJS = main.o Class1.o Class2.o Class3.o Class4.o
HEADERS = Class1.hpp Class2.hpp Class3.hpp Class4.hpp
EXE = main
all: $(EXE)
CXX = g++
CXXFLAGS = -std=c++11 -g -c -Wall
LFLAGS = -Wall -std=c++11 -g
# ---------------------------------------------------------------------
# Rules
# ---------------------------------------------------------------------
RM = rm -rf
.SUFFIXES:
.SUFFIXES: .o .cpp
.cpp.o :
$(CXX) $(CXXFLAGS) -c -o $# $<
$(EXE): $(OBJS)
$(CXX) $(CXXFLAGS) -o $(EXE) $(OBJS)
$(OBJS) : $(HEADERS)
clean:
$(RM) $(OBJS)
$(RM) $(EXE)
again:
make clean
make
And these are the error messages I get when I try to compile:
g++ -std=c++11 -g -c -Wall -o main main.o Class1.o Class2.o Class3.o Class4.o
g++: warning: main.o: linker input file unused because linking not done
g++: warning: Class1.o: linker input file unused because linking not done
g++: warning: Class2.o: linker input file unused because linking not done
g++: warning: Class3.o: linker input file unused because linking not done
g++: warning: Class4.o: linker input file unused because linking not done
I understand that this might be because I'm not linking all the .o files together at the end, but isn't it what this line
$(EXE): $(OBJS)
$(CXX) $(CXXFLAGS) -o $(EXE) $(OBJS)
is supposed to do? Since the -c option is not present.
What am I missing?
Thank you everybody for the help.
Related
I have been trying to link the SFML dlls to my windows C++ project, but I can't get it to work. I always end up with:
fatal error: SFML/System.hpp: No such file or directory
I've tried a bunch of things but nothing changes the issue.
Here is my makefile:
PROGRAM = zero_flip
OBJS = src/main.o src/Math.o src/card.o src/game_board.o src/indicator.o src/ui.o
CXX = g++
CXX_FLAGS = -O0 -g -Wall -Wextra -Wno-unused-parameter -Wno-unused-variable
LIB_DIRS = -L./Resources/libs/
LIBS = -lsfml-system -lsfml-graphics -lsfml-window -lsfml-audio
LNK_FLAGS = $(LIB_DIRS) $(LIBS)
DEPS=$(OBJS:.o=.d)
.PHONY: all clean
all: $(PROGRAM)
-include $(DEPS)
%.o: %.cpp
$(CXX) $(CXX_FLAGS) $(LNK_FLAGS) $< -o $#
$(PROGRAM): $(OBJS)
$(CXX) $(CXX_FLAGS) $(LNK_FLAGS) $^ -o $#
clean:
rm -f $(OBJS) $(DEPS) $(PROGRAM) && clear
The "./Resources/libs/" directory contains:
openal32.dll
sfml-audio-2.dll
sfml-audio-d-2.dll
sfml-graphics-2.dll
sfml-graphics-d-2.dll
sfml-system-2.dll
sfml-system-d-2.dll
sfml-window-2.dll
sfml-window-d-2.dll
Can anyone get me unstuck please this is driving me mad.
This is wrong:
%.o: %.cpp
$(CXX) $(CXX_FLAGS) $(LNK_FLAGS) $< -o $#
This rule says it will compile a source file into an object file, but the recipe actually builds a complete executable: it will compile the source file like xxx.cpp then link it into a program named xxx.o. You need to invoke just the compiler here, not the linker, so you should not have $(LNK_FLAGS) and you need to add the -c option to tell the compiler to stop after compiling and not link.
Then you need to add an -I option to the compile line telling the compiler where to find the header files needed during compilation... in this case SFML/System.hpp.
I am trying to build a Makefile that will build a shared library with g++ and I find that it is not evaluating the OBJECTS variable. This is on Ubuntu 18.04 and all the files are in the same current directory. Secondly it is completely skipping the source file compilation and proceeding directly to evaluate the linking instruction. As a clarification I am using GNU Make 4.1
Here is what I get when I type make all
g++ -shared -pthread -o tree.so
g++: fatal error: no input files
compilation terminated.
Makefile:12: recipe for target 'tree.so' failed
make: *** [tree.so] Error 1
Here is my Makefile code
CC=g++
CFLAGS = -I/usr/local/include -Wall -std=c++17 -O3 -march=native -Ofast -ftree-vectorize
LIBS=-shared -pthread
SOURCES=$(wildcard *.cpp)
OBJECTS=$(wildcard *.o)
TARGET=tree.so
all:$(TARGET)
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(OBJECTS) $(TARGET)
$(OBJECTS):$(SOURCES)
$(CC) -c -g $(CFLAGS) $(SOURCES)
clean:
rm -f $(OBJECTS) $(TARGET)
If you only have the *.cpp files in your directories, then there is not any *.o yet, so your $(wildcard *.o) will expand to nothing.
What you want is to get the *.cpp files and compute the corresponding *.o files:
OBJECTS=$(patsubst %.cpp,%.o,$(SOURCES))
or equivalently:
OBJECTS=$(SOURCES:.cpp=.o)
Now, your compiler command is not the best one, because if you touch any source file all will be compiled. You can use instead:
$(OBJECTS): %.o: %.cpp
$(CC) -c -g $(CFLAGS) $< -o $#
So that only the touched files are actually rebuilt.
Also you have the linking command wrong. It should be:
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(TARGET) $(OBJECTS)
because the argument to the -o option is the output file, that is the target.
EXENAME = prog1
OBJS = link.o main.o
CXX = clang++
CXXFLAGS = -Wall -Wextra
LD = clang++
all : $(EXENAME)
$(EXENAME) : $(OBJS)
$(LD) $(OBJS) -o $(EXENAME)
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) main.cpp
link.o : link.h link.cpp
$(CXX) $(CXXFLAGS) link.cpp
clean :
-rm -f *.o $(EXENAME)
This is the make file I got but all the function in link can't be called in main. I tried many different ways doesn't work. This works
prog1: main.cpp link.h link.cpp
clang++ -Wall -Wextra -o prog1 main.cpp link.cpp
But I suppose is not the right way to do this?
It would help if you provided at least some of the errors you got (probably the first few).
Your compiler invocation for building object files is wrong. Without any other flags specified, the compiler will try to take all the input files and create an executable out of them. So this rule:
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) main.cpp
expands to this compilation line:
clang++ -Wall -Wextra main.cpp
The compiler will attempt to compile and link the main.cpp file (only, because that's all that's listed here) into an executable named a.out (by default).
You need to add the -c option to your compile lines if you want to build an object file rather than link a program:
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) -c main.cpp
Ditto for building link.o.
Even better would be to simply use make's built-in rules for compiling object files rather than writing your own; in that case your entire makefile could just be:
EXENAME = prog1
OBJS = link.o main.o
CXX = clang++
CXXFLAGS = -Wall -Wextra
all : $(EXENAME)
$(EXENAME) : $(OBJS)
$(CXX) $(CXXFLAGS) $(OBJS) -o $(EXENAME)
main.o : link.h
link.o : link.h
clean :
-rm -f *.o $(EXENAME)
As the title states I'm trying to create a makefile for compiling C++ programs using SDL2 on Windows. I have MinGW installed and working. I'm using Sublime 2 as my environment. Here's what I have so far:
CXX = g++
CXXFLAGS = -std=c++0x -g -O3 -w -Wl,-subsystem,windows
INCLFLAGS = -IC:\Libraries\i686-w64-mingw32\include\SDL2
LDFLAGS = -LC:\Libraries\i686-w64-mingw32\lib -lmingw32 -lSDL2main -lSDL2
OBJECTS = main.o
TARGET = 1_hellosdl
$(TARGET) : $(OBJECTS)
$(CXX) $(INCLFLAGS) $(LDFLAGS) $(CXXFLAGS) -o $(TARGET) $(OBJECTS)
main.o :
clean:
rm -rf $(OBJECTS) $(TARGET)
remake:
clean $(TARGET)
Right now when I compile I get the following error:
g++ -std=c++0x -g -O3 -w -Wl,-subsystems,windows -c -o main.o main.cpp
In file included from main.cpp:1:0:
main.hpp:4:17: fatal error: SDL.h: No such file or directory
#include <SDL.h>
So the issue is that g++ can't find the SDL include file when it tries to compile main.cpp. I get that this is because $(INCLFLAGS) isn't being added to the line under main.o :.
Optimally, I'd like to specify INCLFLAGS implicitly similar to CXXFLAGS and LDFLAGS, but based on this it doesn't look like it's possible.
Is there a way to do this using an implicit variable or, failing that, what's the best alternative? Is there anything else I am doing wrong?
I managed to solve this by moving $(INCLFLAGS) into $(CXXFLAGS):
INCLFLAGS = -IC:\Libraries\i686-w64-mingw32\include\SDL2
CXXFLAGS = $(INCLFLAGS) -std=c++0x -g -O3 -w -Wl,-subsystem,windows
Additionally, I had to move $(LDFLAGS) to the end in order for it to link correctly:
$(TARGET) : $(OBJECTS)
$(CXX) $(CXXFLAGS) -o $(TARGET) $(OBJECTS) $(LDFLAGS)
I'm scanning the web and all my project files for solution but still can't find the answer why my linker won't finish the job. Everything smoothly compiles into .o files, but the last make command fails. And here is the Makefile content:
CXX = g++
CXXFLAGS = -Wall -pedantic -c
OBJS = main.o operacje.o porownaj.o
dzialania: $(OBJS)
$(CXX) $^ -o $#
main.o: main.cpp operacje.h porownaj.h
$(CXX) $(CXXFLAGS) $^ -o $#
operacje.o: operacje.cpp operacje.h porownaj.h
$(CXX) $(CXXFLAGS) $^ -o $#
porownaj.o: porownaj.cpp operacje.h porownaj.h
$(CXX) $(CXXFLAGS) $^ -o $#
clean:
rm -f *o
and again, here is the mistake that pops out:
g++ main.o operacje.o porownaj.o -o dzialania
ld: fatal: file main.o: unknown file type
ld: fatal: file processing errors. No output written to dzialania
*** Error code 1
make: Fatal error: Command failed for target `dzialania'
I'm sure it's some kind of a basic mistake but after staring at the file for a few hours I won't notice it anyway. Maybe some of you folks with notice the bug with a fresh eye.
btw. it's my first post after long-term passive lurking, I hope I did everything right. Thanks in advance!
#edit1 OK, I did all the suggested corrections
#edit2 Seems like the problem is caused by improper module division of my program. I'll rearrange it's structure and let you know if it works then. Thanks for all the support!
#edit3 OK, I changed the structure of my program and everything runs smooth, Thanks again!
Try using $< instead of $^ in your rules to compile main.o, operacje.o, and porownaj.o:
main.o: main.cpp operacje.h porownaj.h
$(CXX) $(CXXFLAGS) $< -o $#
operacje.o: operacje.cpp operacje.h porownaj.h
$(CXX) $(CXXFLAGS) $< -o $#
porownaj.o: porownaj.cpp operacje.h porownaj.h
$(CXX) $(CXXFLAGS) $< -o $#
That will cause make to compile only the corresponding .cpp file. When you use $^ the header files are passed to the g++ command which tells the compiler to create precompiled headers for them - that's what's ending up in main.o instead of the object file for main.cpp.
GNU make variable definitions like CC = g++, or CFLAGS = -Wall -pedantic etc.. should each be on its own line:
CC = g++
CFLAGS = -Wall -pedantic
OBJS = main.o operacje.o porownaj.o
BTW, you probably mean
CXX = g++
CXXFLAGS = -Wall -pedantic
You certainly don't want -c explicitly in your CFLAGS or CXXFLAGS; you really should remove it.
Also, recipes should be after its rule, so you want
dzialania: $(OBJS)
$(LINK.cc) $^ -o $#
operacje.o: operacje.cpp operacje.h porownaj.h
$(CXX) $(CXXFLAGS) -c $< -o $#
The several spaces are actually a single tab character.
Run make -p to understand the rules known by make; see also this answer and that one.
Take time to read GNU make documentation.