How do I create a makefile for SDL2/C++ on Windows? - c++

As the title states I'm trying to create a makefile for compiling C++ programs using SDL2 on Windows. I have MinGW installed and working. I'm using Sublime 2 as my environment. Here's what I have so far:
CXX = g++
CXXFLAGS = -std=c++0x -g -O3 -w -Wl,-subsystem,windows
INCLFLAGS = -IC:\Libraries\i686-w64-mingw32\include\SDL2
LDFLAGS = -LC:\Libraries\i686-w64-mingw32\lib -lmingw32 -lSDL2main -lSDL2
OBJECTS = main.o
TARGET = 1_hellosdl
$(TARGET) : $(OBJECTS)
$(CXX) $(INCLFLAGS) $(LDFLAGS) $(CXXFLAGS) -o $(TARGET) $(OBJECTS)
main.o :
clean:
rm -rf $(OBJECTS) $(TARGET)
remake:
clean $(TARGET)
Right now when I compile I get the following error:
g++ -std=c++0x -g -O3 -w -Wl,-subsystems,windows -c -o main.o main.cpp
In file included from main.cpp:1:0:
main.hpp:4:17: fatal error: SDL.h: No such file or directory
#include <SDL.h>
So the issue is that g++ can't find the SDL include file when it tries to compile main.cpp. I get that this is because $(INCLFLAGS) isn't being added to the line under main.o :.
Optimally, I'd like to specify INCLFLAGS implicitly similar to CXXFLAGS and LDFLAGS, but based on this it doesn't look like it's possible.
Is there a way to do this using an implicit variable or, failing that, what's the best alternative? Is there anything else I am doing wrong?

I managed to solve this by moving $(INCLFLAGS) into $(CXXFLAGS):
INCLFLAGS = -IC:\Libraries\i686-w64-mingw32\include\SDL2
CXXFLAGS = $(INCLFLAGS) -std=c++0x -g -O3 -w -Wl,-subsystem,windows
Additionally, I had to move $(LDFLAGS) to the end in order for it to link correctly:
$(TARGET) : $(OBJECTS)
$(CXX) $(CXXFLAGS) -o $(TARGET) $(OBJECTS) $(LDFLAGS)

Related

Makefile does not evaluate OBJECTS variable

I am trying to build a Makefile that will build a shared library with g++ and I find that it is not evaluating the OBJECTS variable. This is on Ubuntu 18.04 and all the files are in the same current directory. Secondly it is completely skipping the source file compilation and proceeding directly to evaluate the linking instruction. As a clarification I am using GNU Make 4.1
Here is what I get when I type make all
g++ -shared -pthread -o tree.so
g++: fatal error: no input files
compilation terminated.
Makefile:12: recipe for target 'tree.so' failed
make: *** [tree.so] Error 1
Here is my Makefile code
CC=g++
CFLAGS = -I/usr/local/include -Wall -std=c++17 -O3 -march=native -Ofast -ftree-vectorize
LIBS=-shared -pthread
SOURCES=$(wildcard *.cpp)
OBJECTS=$(wildcard *.o)
TARGET=tree.so
all:$(TARGET)
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(OBJECTS) $(TARGET)
$(OBJECTS):$(SOURCES)
$(CC) -c -g $(CFLAGS) $(SOURCES)
clean:
rm -f $(OBJECTS) $(TARGET)
If you only have the *.cpp files in your directories, then there is not any *.o yet, so your $(wildcard *.o) will expand to nothing.
What you want is to get the *.cpp files and compute the corresponding *.o files:
OBJECTS=$(patsubst %.cpp,%.o,$(SOURCES))
or equivalently:
OBJECTS=$(SOURCES:.cpp=.o)
Now, your compiler command is not the best one, because if you touch any source file all will be compiled. You can use instead:
$(OBJECTS): %.o: %.cpp
$(CC) -c -g $(CFLAGS) $< -o $#
So that only the touched files are actually rebuilt.
Also you have the linking command wrong. It should be:
$(TARGET) : $(OBJECTS)
$(CC) $(LIBS) -o $(TARGET) $(OBJECTS)
because the argument to the -o option is the output file, that is the target.

Makefile warning: linker input file unused because linking not done

I'm trying to write my own makefile for a C++ program.
I'm editing an old makefile for a C program one of my teacher gave m, but I really don't understand why it keeps telling me that linking is not done.
I have 4 classes with their corresponding headers plus the main file.
This is my makefile:
OBJS = main.o Class1.o Class2.o Class3.o Class4.o
HEADERS = Class1.hpp Class2.hpp Class3.hpp Class4.hpp
EXE = main
all: $(EXE)
CXX = g++
CXXFLAGS = -std=c++11 -g -c -Wall
LFLAGS = -Wall -std=c++11 -g
# ---------------------------------------------------------------------
# Rules
# ---------------------------------------------------------------------
RM = rm -rf
.SUFFIXES:
.SUFFIXES: .o .cpp
.cpp.o :
$(CXX) $(CXXFLAGS) -c -o $# $<
$(EXE): $(OBJS)
$(CXX) $(CXXFLAGS) -o $(EXE) $(OBJS)
$(OBJS) : $(HEADERS)
clean:
$(RM) $(OBJS)
$(RM) $(EXE)
again:
make clean
make
And these are the error messages I get when I try to compile:
g++ -std=c++11 -g -c -Wall -o main main.o Class1.o Class2.o Class3.o Class4.o
g++: warning: main.o: linker input file unused because linking not done
g++: warning: Class1.o: linker input file unused because linking not done
g++: warning: Class2.o: linker input file unused because linking not done
g++: warning: Class3.o: linker input file unused because linking not done
g++: warning: Class4.o: linker input file unused because linking not done
I understand that this might be because I'm not linking all the .o files together at the end, but isn't it what this line
$(EXE): $(OBJS)
$(CXX) $(CXXFLAGS) -o $(EXE) $(OBJS)
is supposed to do? Since the -c option is not present.
What am I missing?
Thank you everybody for the help.

C++ makefile not linking

EXENAME = prog1
OBJS = link.o main.o
CXX = clang++
CXXFLAGS = -Wall -Wextra
LD = clang++
all : $(EXENAME)
$(EXENAME) : $(OBJS)
$(LD) $(OBJS) -o $(EXENAME)
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) main.cpp
link.o : link.h link.cpp
$(CXX) $(CXXFLAGS) link.cpp
clean :
-rm -f *.o $(EXENAME)
This is the make file I got but all the function in link can't be called in main. I tried many different ways doesn't work. This works
prog1: main.cpp link.h link.cpp
clang++ -Wall -Wextra -o prog1 main.cpp link.cpp
But I suppose is not the right way to do this?
It would help if you provided at least some of the errors you got (probably the first few).
Your compiler invocation for building object files is wrong. Without any other flags specified, the compiler will try to take all the input files and create an executable out of them. So this rule:
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) main.cpp
expands to this compilation line:
clang++ -Wall -Wextra main.cpp
The compiler will attempt to compile and link the main.cpp file (only, because that's all that's listed here) into an executable named a.out (by default).
You need to add the -c option to your compile lines if you want to build an object file rather than link a program:
main.o : link.h main.cpp
$(CXX) $(CXXFLAGS) -c main.cpp
Ditto for building link.o.
Even better would be to simply use make's built-in rules for compiling object files rather than writing your own; in that case your entire makefile could just be:
EXENAME = prog1
OBJS = link.o main.o
CXX = clang++
CXXFLAGS = -Wall -Wextra
all : $(EXENAME)
$(EXENAME) : $(OBJS)
$(CXX) $(CXXFLAGS) $(OBJS) -o $(EXENAME)
main.o : link.h
link.o : link.h
clean :
-rm -f *.o $(EXENAME)

SDL Max OSX via Homebrew, Makefile not quite working

I have installed SDL through homebrew, and it works perfectly with my test program if I enter the following command directly in the terminal:
g++ -O3 -g -Wall -Wextra -std=c++1y hello.cpp hello_main.cpp `sdl2-config --cflags --libs` -o hello
but unfortunately my attempts to write a makefile (I will definitely need one) have yielded unsuccessful/unexplained results.
I am following this, but my configuration is different/I am not specifying Cocoa (I don't need to) so I expect that the issues I am encountering are probably due in part to my different requirements:
Compiling SDL on OS X with makefile
Example:
CC=g++
CFLAGS=-c -Wall
SDLFLAGS=`sdl-config --cflags --libs` -framework Cocoa
SOURCES=main.cpp Game.cpp IO.cpp Board.cpp Pieces.cpp Piece.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=tetris
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(OBJECTS) $(SDLFLAGS) -o $#
.cpp.o:
$(CC) $(CFLAGS) $< -o $#
clean:
rm -rf *.o $(EXECUTABLE)
My makefile so far:
CXX = g++
CXXFLAGS = -c -O3 -g -Wall -Wextra -std=c++1y
SDLFLAGS = `sdl2-config --cflags --libs`
SOURCES = hello_main.cpp hello.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECNAME = hello
all: $(SOURCES) $(EXECNAME)
$(EXECUTABLE): $(OBJECTS)
$(CXX) $ (OBJECTS) $(SDLFLAGS) -o $#
.cpp.o:
$(CXX) $(CXXFLAGS) $< -o $#
clean :
-rm -f *.o *.core $(EXECNAME)
In my .hpp header file if I #include <SDL.h> and run the one-liner command, everything is successful. If I try my makefile above, cannot be found, but if I then change the directive into #include <SDL2/SDL.h> the library is discovered. Yet the console output is the following:
g++ -c -O3 -g -Wall -Wextra -std=c++1y hello.cpp -o hello
which is odd.
Running ./hello yields a "permission denied" error, which confirms that the linking and compilation were not successful.
Everyone's system is a little bit different and the questions I've found so far don't help in this case.
I am very close to having this working (but then again, how would I start using this in an IDE? I suppose that as long as I can import the fixed makefile or build from the terminal/edit only from the IDE, I am fine.)
What changes in the makefile do I need to make?
Thank you.
EDIT:
Variation 1:
CXX = g++
CXXFLAGS = -O3 -g -Wall -Wextra -std=c++1y -c
SDLCFLAGS = `sdl2-config --cflags`
SDLLIBFLAGS = `sdl2-config --libs`
SOURCES = hello_main.cpp hello.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECNAME = hello
all: $(SOURCES) $(EXECNAME)
$(EXECUTABLE): $(OBJECTS)
$(CXX) $ (OBJECTS) $(SDLLIBFLAGS) -o $#
.cpp.o:
$(CXX) $(CXXFLAGS) $(SDLCFLAGS) $< -o $#
clean :
-rm -f *.o *.core $(EXECNAME)
I chatted with a friend and figured what was wrong: a bunch of typos and rule oddities. The following works, for anyone out there who needs a basic makefile:
CXX = g++
CXXFLAGS = -O3 -g -Wall -Wextra -std=c++1y
#LDFLAGS = -lSDL2_image
SDLCFLAGS = $(shell sdl2-config --cflags)
SDLLIBFLAGS = $(shell sdl2-config --libs)
SOURCES = hello_main.cpp hello.cpp
OBJECTS = $(SOURCES:.cpp=.o)
EXECNAME = hello
all: $(EXECNAME)
$(EXECNAME): $(OBJECTS)
$(CXX) $(OBJECTS) $(SDLLIBFLAGS) $(LDFLAGS) -o $#
%.o: %.cpp
$(CXX) -c $(CXXFLAGS) $(SDLCFLAGS) $< -o $#
clean :
-rm -f *.o *.core $(EXECNAME)
You should split your sdl2-config into two - as there are two steps. sdl2-config --cflags should go in the compiler step - thats is the .cpp:.o line in your example. The linking step should be sdl2-config --libs then. The second one seems fine for your case, the additional --cflags there does no harm but is not required.

how do I set compilingflags in a makefile?

I'm used to program in IDEs, but switched to vim and plugins recently. Now I try to write a makefile for a c++ project, but somehow if I run make I always get the error
g++ -c -o *.o createOutput.cpp
In file included from /usr/include/c++/4.8/thread:35:0,
from createOutput.cpp:5:
/usr/include/c++/4.8/bits/c++0x_warning.h:32:2: error: #error This file requires compiler and library support for the ISO C++ 2011 standard. This support is currently experimental, and must be enabled with the -std=c++11 or -std=gnu++11 compiler options.
#error This file requires compiler and library support for the \
^
This is my makefile:
CC = clang++
# compiler flags
CFLAGS = -O3 -Wall -Werror -std=c++11
CFLAGS_SFML = -lsfml-graphics -lsfml-window -lsfml-system
all: program.exe clean
program.exe: *.o
$(CC) -o program.exe *.o $(CFLAGS) $(CFLAGS_SFML)
getInput.o: getInput.cpp
$(CC) -c getInput.cpp $(CFLAGS)
createOutput.o: createOutput.cpp
$(CC) -c createOutput.cpp $(CFLAGS)
main.o: main.cpp
$(CC) -c main.cpp $(CFLAGS)
.PHONY: clean
clean:
rm *.o
#echo clean done
Where is my error? Why is it using g++ instead of clang? And why isn't it using the -std=c++11 parameter? Sorry for the beginner questions, I unfortunately can't find a solution with google.
You want to set CXXFLAGS, that gets picked up automatically by make (and sent to your compiler (eg g++, clang++, etc).
make tried to make target '*.o'.
So, instead of that, you can specify sources list explicitly:
CC = clang++
#compiler flags
CFLAGS = -O3 -Wall -Werror -std=c++11
CFLAGS_SFML = -lsfml-graphics -lsfml-window -lsfml-system
SRCS = getInput.cpp createOutput.cpp main.cpp
OBJS = $(SRCS:.cpp=.o)
all: program.exe
program.exe: $(OBJS)
$(CC) -o program.exe *.o $(CFLAGS) $(CFLAGS_SFML)
getInput.o: getInput.cpp
$(CC) -c getInput.cpp $(CFLAGS)
createOutput.o: createOutput.cpp
$(CC) -c createOutput.cpp $(CFLAGS)
main.o: main.cpp
$(CC) -c main.cpp $(CFLAGS)
.PHONY : clean
clean:
rm *.o
#echo clean done
Note definition of variables OBJS and SRCS.