Verilog 4-bit carry select adder - if-statement

Question

So I am trying to design a 4-bit carry select adder in verilog, and am using the following code for the design:
module fullAdder (S,Cout,P,G,A,B,Cin);
// Define all inputs and outputs for single bit Fulll Adder
output S;
output Cout;
output P;
output G;
input A;
input B;
input Cin;
// Full Adder body, define structure and internal wiring
wire t1, t2, t3;
xor xor1 (t1, A, B);
xor xor2 (S, t1, Cin);
or or1 (P, A, B);
and and1 (G, A, B);
and and2 (t2, P, Cin);
or or2 (Cout, t2, G);
endmodule
module carrySelect (sum, cout, a, b, cin);
output [3:0] sum; //sum output of the adder, 4 bits wide
output cout; //carry out of the adder
input [3:0] a; //input a, 4 bits wide
input [3:0] b; //input b, 4 bits wide
input cin; //carry in of the adder
reg ch, cl; //temporary variables to define cases that previous carry is high or low
wire [3:0] C; //carry bus
wire [3:0] P,G; //buses for P and G outputs of fullAdder
wire [1:0] s0, s1, s2, s3; //temporary buses for cases of sums
wire [1:0] c0, c1, c2, c3; //temporary buses for cases of carries
assign ch = 1; //assign ch to high and cl to low
assign cl = 0;
//least significant full adder computation
fullAdder f0_h (s0[0],c0[0],p0[0], g0[0], a[0], b[0], ch);
fullAdder f0_l (s0[1],c0[1],p0[1], g0[1], a[0], b[0], cl);
fullAdder f1_h (s1[0],c1[0],p1[0], g1[0], a[0], b[0], ch);
fullAdder f1_l(s1[1],c1[1],p1[1], g1[1], a[0], b[0], cl);
fullAdder f2_h (s2[0],c2[0],p2[0], g2[0], a[0], b[0], ch);
fullAdder f2_l (s2[1],c2[1],p2[1], g2[1], a[0], b[0], cl);
//most significant full adder computation
fullAdder f3_h (s3[0],c3[0],p3[0], g3[0], a[0], b[0], ch);
fullAdder f3_l (s3[1],c3[1],p3[1], g3[1], a[0], b[0], cl);
//select output depending on values of carries
if (cin == 1) begin
assign sum[0] = s0[0];
assign C[0] = c0[0];
end else begin
assign sum[0] = s0[1];
assign C[0] = c0[1];
end
if(C[0] == 1) begin
assign sum[1] = s1[0];
assign C[1] = c1[0];
end else begin
assign sum[1] = s1[1];
assign C[1] = c1[1];
end
if(C[1]) begin
assign sum[2] = s2[0];
assign C[2] = c2[0];
end else begin
assign sum[2] = s2[1];
assign C[2] = c2[1];
end
if(C[2]) begin
assign sum[3] = s3[0];
assign C[3] = c3[0];
end else begin
assign sum[3] = s3[1];
assign C[3] = c3[1];
end
//assign carry out
assign cout = C[3];
endmodule
where the full adder is completely functional, so there are no problems there. I get errors from the if statements when I try to compile the code, and get the warning about implicit definitions and error of not being able to evaluate genvar of the conditional in the ifs. I am fairly new to verilog, so I apologize if this is a trivial fix. Any help is appreciated.
EDIT1:Error/warning message thrown
design.sv:57: warning: implicit definition of wire fullAdderTest.UUT.cin.
design.sv:57: error: Cannot evaluate genvar conditional expression: (cin)==('sd1)
design.sv:57: error: Cannot evaluate genvar conditional expression: (cin)==('sd1)
design.sv:65: warning: implicit definition of wire fullAdderTest.UUT.C.
design.sv:65: error: Cannot evaluate genvar conditional expression: (C['sd0])==('sd1)
design.sv:65: error: Cannot evaluate genvar conditional expression: (C['sd0])==('sd1)
design.sv:73: warning: Constant bit select [1] is after vector C[0:0].
design.sv:73: : Replacing select with a constant 1'bx.
design.sv:73: warning: Constant bit select [1] is after vector C[0:0].
design.sv:73: : Replacing select with a constant 1'bx.
design.sv:81: warning: Constant bit select [2] is after vector C[0:0].
design.sv:81: : Replacing select with a constant 1'bx.
design.sv:81: warning: Constant bit select [2] is after vector C[0:0].
design.sv:81: : Replacing select with a constant 1'bx.
4 error(s) during elaboration.

Answer 1

An if statement outside of an always or initial block is treated as a if it was inside an generate block. A generate's if statement will accepts literal constants (hard coded values), parameters, and genvars. It will not accept net or register types (i.e: wire, reg, integer, etc). Generate blocks are evaluated during elaboration and therefore cannot depend on simulation variables with dynamic values.
You want conditionally select the values for sum and C based on input values. There are a few options to do this:
One option is to make an inline condition statement:
assign sum[0] = cin ? s0[0] : s0[1];
assign C[0] = cin ? c0[0] : c0[1];
// ...
Or you can select the index (same effect):
assign sum[0] = s0[!cin];
assign C[0] = c0[!cin];
assign sum[1] = s1[!C[0]];
assign C[1] = c1[!C[0]];
// ...
Or make sum and C reg types and put all the if statements inside an always block (remove the assigns):
always #* begin
if (cin == 1) begin
sum[0] = s0[0];
C[0] = c0[0];
end
else begin
sum[0] = s0[1];
C[0] = c0[1];
end
// ...
end